minmax.t2_fixed.smt2

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details
attribute value
description
owner Johannes Waldmann
uploaded 2017-08-17 03:45:05.0
disk size 14.26 KB
downloadable true
type
attribute value
name no_type
processor id 1
description this is the default benchmark type for rejected benchmarks and benchmarks that are not associated with a type.
owning community none
loading contents
(declare-sort Loc 0)
(declare-const l0 Loc)
(declare-const l1 Loc)
(declare-const l2 Loc)
(declare-const l3 Loc)
(declare-const l4 Loc)
(declare-const l5 Loc)
(declare-const l6 Loc)
(declare-const l7 Loc)
(declare-const l8 Loc)
(declare-const l9 Loc)
(declare-const l10 Loc)
(declare-const l11 Loc)
(declare-const l12 Loc)
(declare-const l13 Loc)
(assert (distinct l0 l1 l2 l3 l4 l5 l6 l7 l8 l9 l10 l11 l12 l13))

(define-fun cfg_init ( (pc Loc) (src Loc) (rel Bool) ) Bool
  (and (= pc src) rel))

(define-fun cfg_trans2 ( (pc Loc) (src Loc)
                         (pc1 Loc) (dst Loc)
                         (rel Bool) ) Bool
  (and (= pc src) (= pc1 dst) rel))

(define-fun cfg_trans3 ( (pc Loc) (exit Loc)
                         (pc1 Loc) (call Loc)
                         (pc2 Loc) (return Loc)
                         (rel Bool) ) Bool
  (and (= pc exit) (= pc1 call) (= pc2 return) rel))

(define-fun init_main ( (pc^0 Loc) (a10^0 Int) (a15^0 Int) (b11^0 Int) (b16^0 Int) (c12^0 Int) (c17^0 Int) (m13^0 Int) (ret_max24^0 Int) (ret_min14^0 Int) (tmp620^0 Int) (tmp923^0 Int) (tmp9^0 Int) (tmp^0 Int) (tmp___0^0 Int) (tmp___1^0 Int) (x_promoted_1^0 Int) (y_promoted_2^0 Int) (z^0 Int) ) Bool
  (cfg_init pc^0 l13 true))

(define-fun next_main (
                 (pc^0 Loc) (a10^0 Int) (a15^0 Int) (b11^0 Int) (b16^0 Int) (c12^0 Int) (c17^0 Int) (m13^0 Int) (ret_max24^0 Int) (ret_min14^0 Int) (tmp620^0 Int) (tmp923^0 Int) (tmp9^0 Int) (tmp^0 Int) (tmp___0^0 Int) (tmp___1^0 Int) (x_promoted_1^0 Int) (y_promoted_2^0 Int) (z^0 Int)
                 (pc^post Loc) (a10^post Int) (a15^post Int) (b11^post Int) (b16^post Int) (c12^post Int) (c17^post Int) (m13^post Int) (ret_max24^post Int) (ret_min14^post Int) (tmp620^post Int) (tmp923^post Int) (tmp9^post Int) (tmp^post Int) (tmp___0^post Int) (tmp___1^post Int) (x_promoted_1^post Int) (y_promoted_2^post Int) (z^post Int)
             ) Bool
  (or
    (cfg_trans2 pc^0 l0 pc^post l1 (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (= a10^0 a10^post) (= a15^0 a15^post)) (= b11^0 b11^post)) (= b16^0 b16^post)) (= c12^0 c12^post)) (= c17^0 c17^post)) (= m13^0 m13^post)) (= ret_max24^0 ret_max24^post)) (= ret_min14^0 ret_min14^post)) (= tmp^0 tmp^post)) (= tmp620^0 tmp620^post)) (= tmp9^0 tmp9^post)) (= tmp923^0 tmp923^post)) (= tmp___0^0 tmp___0^post)) (= tmp___1^0 tmp___1^post)) (= x_promoted_1^0 x_promoted_1^post)) (= y_promoted_2^0 y_promoted_2^post)) (= z^0 z^post)))
    (cfg_trans2 pc^0 l2 pc^post l3 (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (= ret_max24^post (+ 0 a15^0)) (= tmp___0^post (+ 0 ret_max24^post))) (= z^post z^post)) (= a10^0 a10^post)) (= a15^0 a15^post)) (= b11^0 b11^post)) (= b16^0 b16^post)) (= c12^0 c12^post)) (= c17^0 c17^post)) (= m13^0 m13^post)) (= ret_min14^0 ret_min14^post)) (= tmp^0 tmp^post)) (= tmp620^0 tmp620^post)) (= tmp9^0 tmp9^post)) (= tmp923^0 tmp923^post)) (= tmp___1^0 tmp___1^post)) (= x_promoted_1^0 x_promoted_1^post)) (= y_promoted_2^0 y_promoted_2^post)))
    (cfg_trans2 pc^0 l4 pc^post l5 (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (<= (+ 1 y_promoted_2^0) (+ 0 x_promoted_1^0)) (= a10^0 a10^post)) (= a15^0 a15^post)) (= b11^0 b11^post)) (= b16^0 b16^post)) (= c12^0 c12^post)) (= c17^0 c17^post)) (= m13^0 m13^post)) (= ret_max24^0 ret_max24^post)) (= ret_min14^0 ret_min14^post)) (= tmp^0 tmp^post)) (= tmp620^0 tmp620^post)) (= tmp9^0 tmp9^post)) (= tmp923^0 tmp923^post)) (= tmp___0^0 tmp___0^post)) (= tmp___1^0 tmp___1^post)) (= x_promoted_1^0 x_promoted_1^post)) (= y_promoted_2^0 y_promoted_2^post)) (= z^0 z^post)))
    (cfg_trans2 pc^0 l4 pc^post l3 (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (<= (+ 0 x_promoted_1^0) (+ 0 y_promoted_2^0)) (= tmp9^post tmp9^post)) (= a10^0 a10^post)) (= a15^0 a15^post)) (= b11^0 b11^post)) (= b16^0 b16^post)) (= c12^0 c12^post)) (= c17^0 c17^post)) (= m13^0 m13^post)) (= ret_max24^0 ret_max24^post)) (= ret_min14^0 ret_min14^post)) (= tmp^0 tmp^post)) (= tmp620^0 tmp620^post)) (= tmp923^0 tmp923^post)) (= tmp___0^0 tmp___0^post)) (= tmp___1^0 tmp___1^post)) (= x_promoted_1^0 x_promoted_1^post)) (= y_promoted_2^0 y_promoted_2^post)) (= z^0 z^post)))
    (cfg_trans2 pc^0 l6 pc^post l2 (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (<= (+ 1 c17^0) (+ 0 a15^0)) (= a10^0 a10^post)) (= a15^0 a15^post)) (= b11^0 b11^post)) (= b16^0 b16^post)) (= c12^0 c12^post)) (= c17^0 c17^post)) (= m13^0 m13^post)) (= ret_max24^0 ret_max24^post)) (= ret_min14^0 ret_min14^post)) (= tmp^0 tmp^post)) (= tmp620^0 tmp620^post)) (= tmp9^0 tmp9^post)) (= tmp923^0 tmp923^post)) (= tmp___0^0 tmp___0^post)) (= tmp___1^0 tmp___1^post)) (= x_promoted_1^0 x_promoted_1^post)) (= y_promoted_2^0 y_promoted_2^post)) (= z^0 z^post)))
    (cfg_trans2 pc^0 l6 pc^post l2 (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (<= (+ 0 a15^0) (+ 0 c17^0)) (= tmp923^post tmp923^post)) (= a10^0 a10^post)) (= a15^0 a15^post)) (= b11^0 b11^post)) (= b16^0 b16^post)) (= c12^0 c12^post)) (= c17^0 c17^post)) (= m13^0 m13^post)) (= ret_max24^0 ret_max24^post)) (= ret_min14^0 ret_min14^post)) (= tmp^0 tmp^post)) (= tmp620^0 tmp620^post)) (= tmp9^0 tmp9^post)) (= tmp___0^0 tmp___0^post)) (= tmp___1^0 tmp___1^post)) (= x_promoted_1^0 x_promoted_1^post)) (= y_promoted_2^0 y_promoted_2^post)) (= z^0 z^post)))
    (cfg_trans2 pc^0 l7 pc^post l6 (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (<= (+ 1 b16^0) (+ 0 a15^0)) (= a10^0 a10^post)) (= a15^0 a15^post)) (= b11^0 b11^post)) (= b16^0 b16^post)) (= c12^0 c12^post)) (= c17^0 c17^post)) (= m13^0 m13^post)) (= ret_max24^0 ret_max24^post)) (= ret_min14^0 ret_min14^post)) (= tmp^0 tmp^post)) (= tmp620^0 tmp620^post)) (= tmp9^0 tmp9^post)) (= tmp923^0 tmp923^post)) (= tmp___0^0 tmp___0^post)) (= tmp___1^0 tmp___1^post)) (= x_promoted_1^0 x_promoted_1^post)) (= y_promoted_2^0 y_promoted_2^post)) (= z^0 z^post)))
    (cfg_trans2 pc^0 l7 pc^post l6 (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (<= (+ 0 a15^0) (+ 0 b16^0)) (= tmp620^post tmp620^post)) (= a10^0 a10^post)) (= a15^0 a15^post)) (= b11^0 b11^post)) (= b16^0 b16^post)) (= c12^0 c12^post)) (= c17^0 c17^post)) (= m13^0 m13^post)) (= ret_max24^0 ret_max24^post)) (= ret_min14^0 ret_min14^post)) (= tmp^0 tmp^post)) (= tmp9^0 tmp9^post)) (= tmp923^0 tmp923^post)) (= tmp___0^0 tmp___0^post)) (= tmp___1^0 tmp___1^post)) (= x_promoted_1^0 x_promoted_1^post)) (= y_promoted_2^0 y_promoted_2^post)) (= z^0 z^post)))
    (cfg_trans2 pc^0 l8 pc^post l9 (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (<= (+ 1 c12^0) (+ 0 b11^0)) (= m13^post (+ 0 c12^0))) (= a10^0 a10^post)) (= a15^0 a15^post)) (= b11^0 b11^post)) (= b16^0 b16^post)) (= c12^0 c12^post)) (= c17^0 c17^post)) (= ret_max24^0 ret_max24^post)) (= ret_min14^0 ret_min14^post)) (= tmp^0 tmp^post)) (= tmp620^0 tmp620^post)) (= tmp9^0 tmp9^post)) (= tmp923^0 tmp923^post)) (= tmp___0^0 tmp___0^post)) (= tmp___1^0 tmp___1^post)) (= x_promoted_1^0 x_promoted_1^post)) (= y_promoted_2^0 y_promoted_2^post)) (= z^0 z^post)))
    (cfg_trans2 pc^0 l8 pc^post l9 (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (<= (+ 0 b11^0) (+ 0 c12^0)) (= m13^post (+ 0 b11^0))) (= a10^0 a10^post)) (= a15^0 a15^post)) (= b11^0 b11^post)) (= b16^0 b16^post)) (= c12^0 c12^post)) (= c17^0 c17^post)) (= ret_max24^0 ret_max24^post)) (= ret_min14^0 ret_min14^post)) (= tmp^0 tmp^post)) (= tmp620^0 tmp620^post)) (= tmp9^0 tmp9^post)) (= tmp923^0 tmp923^post)) (= tmp___0^0 tmp___0^post)) (= tmp___1^0 tmp___1^post)) (= x_promoted_1^0 x_promoted_1^post)) (= y_promoted_2^0 y_promoted_2^post)) (= z^0 z^post)))
    (cfg_trans2 pc^0 l9 pc^post l3 (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (= ret_min14^post (+ 0 m13^0)) (= tmp^post (+ 0 ret_min14^post))) (= x_promoted_1^post (+ (+ 0 tmp^post) x_promoted_1^0))) (= a10^0 a10^post)) (= a15^0 a15^post)) (= b11^0 b11^post)) (= b16^0 b16^post)) (= c12^0 c12^post)) (= c17^0 c17^post)) (= m13^0 m13^post)) (= ret_max24^0 ret_max24^post)) (= tmp620^0 tmp620^post)) (= tmp9^0 tmp9^post)) (= tmp923^0 tmp923^post)) (= tmp___0^0 tmp___0^post)) (= tmp___1^0 tmp___1^post)) (= y_promoted_2^0 y_promoted_2^post)) (= z^0 z^post)))
    (cfg_trans2 pc^0 l10 pc^post l9 (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (<= (+ 1 c12^0) (+ 0 a10^0)) (= m13^post (+ 0 c12^0))) (= a10^0 a10^post)) (= a15^0 a15^post)) (= b11^0 b11^post)) (= b16^0 b16^post)) (= c12^0 c12^post)) (= c17^0 c17^post)) (= ret_max24^0 ret_max24^post)) (= ret_min14^0 ret_min14^post)) (= tmp^0 tmp^post)) (= tmp620^0 tmp620^post)) (= tmp9^0 tmp9^post)) (= tmp923^0 tmp923^post)) (= tmp___0^0 tmp___0^post)) (= tmp___1^0 tmp___1^post)) (= x_promoted_1^0 x_promoted_1^post)) (= y_promoted_2^0 y_promoted_2^post)) (= z^0 z^post)))
    (cfg_trans2 pc^0 l10 pc^post l9 (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (<= (+ 0 a10^0) (+ 0 c12^0)) (= m13^post (+ 0 a10^0))) (= a10^0 a10^post)) (= a15^0 a15^post)) (= b11^0 b11^post)) (= b16^0 b16^post)) (= c12^0 c12^post)) (= c17^0 c17^post)) (= ret_max24^0 ret_max24^post)) (= ret_min14^0 ret_min14^post)) (= tmp^0 tmp^post)) (= tmp620^0 tmp620^post)) (= tmp9^0 tmp9^post)) (= tmp923^0 tmp923^post)) (= tmp___0^0 tmp___0^post)) (= tmp___1^0 tmp___1^post)) (= x_promoted_1^0 x_promoted_1^post)) (= y_promoted_2^0 y_promoted_2^post)) (= z^0 z^post)))
    (cfg_trans2 pc^0 l11 pc^post l8 (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (<= (+ 1 b11^0) (+ 0 a10^0)) (= a10^0 a10^post)) (= a15^0 a15^post)) (= b11^0 b11^post)) (= b16^0 b16^post)) (= c12^0 c12^post)) (= c17^0 c17^post)) (= m13^0 m13^post)) (= ret_max24^0 ret_max24^post)) (= ret_min14^0 ret_min14^post)) (= tmp^0 tmp^post)) (= tmp620^0 tmp620^post)) (= tmp9^0 tmp9^post)) (= tmp923^0 tmp923^post)) (= tmp___0^0 tmp___0^post)) (= tmp___1^0 tmp___1^post)) (= x_promoted_1^0 x_promoted_1^post)) (= y_promoted_2^0 y_promoted_2^post)) (= z^0 z^post)))
    (cfg_trans2 pc^0 l11 pc^post l10 (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (<= (+ 0 a10^0) (+ 0 b11^0)) (= a10^0 a10^post)) (= a15^0 a15^post)) (= b11^0 b11^post)) (= b16^0 b16^post)) (= c12^0 c12^post)) (= c17^0 c17^post)) (= m13^0 m13^post)) (= ret_max24^0 ret_max24^post)) (= ret_min14^0 ret_min14^post)) (= tmp^0 tmp^post)) (= tmp620^0 tmp620^post)) (= tmp9^0 tmp9^post)) (= tmp923^0 tmp923^post)) (= tmp___0^0 tmp___0^post)) (= tmp___1^0 tmp___1^post)) (= x_promoted_1^0 x_promoted_1^post)) (= y_promoted_2^0 y_promoted_2^post)) (= z^0 z^post)))
    (cfg_trans2 pc^0 l5 pc^post l7 (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (<= (+ 1 z^0) (+ 0 x_promoted_1^0)) (= a15^post (+ 0 z^0))) (= b16^post (+ 0 y_promoted_2^0))) (= c17^post (+ 0 x_promoted_1^0))) (= a10^0 a10^post)) (= b11^0 b11^post)) (= c12^0 c12^post)) (= m13^0 m13^post)) (= ret_max24^0 ret_max24^post)) (= ret_min14^0 ret_min14^post)) (= tmp^0 tmp^post)) (= tmp620^0 tmp620^post)) (= tmp9^0 tmp9^post)) (= tmp923^0 tmp923^post)) (= tmp___0^0 tmp___0^post)) (= tmp___1^0 tmp___1^post)) (= x_promoted_1^0 x_promoted_1^post)) (= y_promoted_2^0 y_promoted_2^post)) (= z^0 z^post)))
    (cfg_trans2 pc^0 l5 pc^post l11 (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (<= (+ 0 x_promoted_1^0) (+ 0 z^0)) (= a10^post (+ 0 x_promoted_1^0))) (= b11^post (+ 0 y_promoted_2^0))) (= c12^post (+ 0 z^0))) (= a15^0 a15^post)) (= b16^0 b16^post)) (= c17^0 c17^post)) (= m13^0 m13^post)) (= ret_max24^0 ret_max24^post)) (= ret_min14^0 ret_min14^post)) (= tmp^0 tmp^post)) (= tmp620^0 tmp620^post)) (= tmp9^0 tmp9^post)) (= tmp923^0 tmp923^post)) (= tmp___0^0 tmp___0^post)) (= tmp___1^0 tmp___1^post)) (= x_promoted_1^0 x_promoted_1^post)) (= y_promoted_2^0 y_promoted_2^post)) (= z^0 z^post)))
    (cfg_trans2 pc^0 l3 pc^post l0 (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (<= (+ 1 z^0) (+ 0 y_promoted_2^0)) (= tmp___1^post (+ (+ 0 y_promoted_2^0) (* -1 z^0)))) (= a10^0 a10^post)) (= a15^0 a15^post)) (= b11^0 b11^post)) (= b16^0 b16^post)) (= c12^0 c12^post)) (= c17^0 c17^post)) (= m13^0 m13^post)) (= ret_max24^0 ret_max24^post)) (= ret_min14^0 ret_min14^post)) (= tmp^0 tmp^post)) (= tmp620^0 tmp620^post)) (= tmp9^0 tmp9^post)) (= tmp923^0 tmp923^post)) (= tmp___0^0 tmp___0^post)) (= x_promoted_1^0 x_promoted_1^post)) (= y_promoted_2^0 y_promoted_2^post)) (= z^0 z^post)))
    (cfg_trans2 pc^0 l3 pc^post l0 (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (<= (+ 0 y_promoted_2^0) (+ 0 z^0)) (= tmp___1^post (+ (+ 0 y_promoted_2^0) z^0))) (= a10^0 a10^post)) (= a15^0 a15^post)) (= b11^0 b11^post)) (= b16^0 b16^post)) (= c12^0 c12^post)) (= c17^0 c17^post)) (= m13^0 m13^post)) (= ret_max24^0 ret_max24^post)) (= ret_min14^0 ret_min14^post)) (= tmp^0 tmp^post)) (= tmp620^0 tmp620^post)) (= tmp9^0 tmp9^post)) (= tmp923^0 tmp923^post)) (= tmp___0^0 tmp___0^post)) (= x_promoted_1^0 x_promoted_1^post)) (= y_promoted_2^0 y_promoted_2^post)) (= z^0 z^post)))
    (cfg_trans2 pc^0 l12 pc^post l4 (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (= x_promoted_1^post 10) (= y_promoted_2^post 2)) (= z^post 1)) (= a10^0 a10^post)) (= a15^0 a15^post)) (= b11^0 b11^post)) (= b16^0 b16^post)) (= c12^0 c12^post)) (= c17^0 c17^post)) (= m13^0 m13^post)) (= ret_max24^0 ret_max24^post)) (= ret_min14^0 ret_min14^post)) (= tmp^0 tmp^post)) (= tmp620^0 tmp620^post)) (= tmp9^0 tmp9^post)) (= tmp923^0 tmp923^post)) (= tmp___0^0 tmp___0^post)) (= tmp___1^0 tmp___1^post)))
    (cfg_trans2 pc^0 l13 pc^post l12 (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (and (= a10^0 a10^post) (= a15^0 a15^post)) (= b11^0 b11^post)) (= b16^0 b16^post)) (= c12^0 c12^post)) (= c17^0 c17^post)) (= m13^0 m13^post)) (= ret_max24^0 ret_max24^post)) (= ret_min14^0 ret_min14^post)) (= tmp^0 tmp^post)) (= tmp620^0 tmp620^post)) (= tmp9^0 tmp9^post)) (= tmp923^0 tmp923^post)) (= tmp___0^0 tmp___0^post)) (= tmp___1^0 tmp___1^post)) (= x_promoted_1^0 x_promoted_1^post)) (= y_promoted_2^0 y_promoted_2^post)) (= z^0 z^post)))
  )
)
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