details

property	value
status	complete
benchmark	PEANO_nosorts-noand_FR.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n090.star.cs.uiowa.edu
space	Transformed_CSR_04

run statistics

property	value
solver	AProVE
configuration	standard
runtime (wallclock)	1.56591200829 seconds
cpu usage	3.593394279
max memory	2.28667392E8

stage attributes

key	value
output-size	1796
starexec-result	YES

output

/export/starexec/sandbox2/solver/bin/starexec_run_standard /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES proof of /export/starexec/sandbox2/benchmark/theBenchmark.xml # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty Termination w.r.t. Q of the given QTRS could be proven: (0) QTRS (1) QTRSRRRProof [EQUIVALENT, 0 ms] (2) QTRS (3) RisEmptyProof [EQUIVALENT, 0 ms] (4) YES ---------------------------------------- (0) Obligation: Q restricted rewrite system: The TRS R consists of the following rules: U11(tt, M, N) -> U12(tt, activate(M), activate(N)) U12(tt, M, N) -> s(plus(activate(N), activate(M))) plus(N, 0) -> N plus(N, s(M)) -> U11(tt, M, N) activate(X) -> X Q is empty. ---------------------------------------- (1) QTRSRRRProof (EQUIVALENT) Used ordering: Knuth-Bendix order [KBO] with precedence:activate_1 > plus_2 > U11_3 > U12_3 > s_1 > 0 > tt and weight map: tt=2 0=1 activate_1=0 s_1=1 U11_3=0 U12_3=0 plus_2=1 The variable weight is 1With this ordering the following rules can be removed by the rule removal processor [LPAR04] because they are oriented strictly: U11(tt, M, N) -> U12(tt, activate(M), activate(N)) U12(tt, M, N) -> s(plus(activate(N), activate(M))) plus(N, 0) -> N plus(N, s(M)) -> U11(tt, M, N) activate(X) -> X ---------------------------------------- (2) Obligation: Q restricted rewrite system: R is empty. Q is empty. ---------------------------------------- (3) RisEmptyProof (EQUIVALENT) The TRS R is empty. Hence, termination is trivially proven. ---------------------------------------- (4) YES popout

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job log

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actions

all output return to TRS Stand 20472