details

property	value
status	complete
benchmark	PEANO_nokinds-noand_Z.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n033.star.cs.uiowa.edu
space	Transformed_CSR_04

run statistics

property	value
solver	ttt2-1.17+nonreach
configuration	ttt2-1.17+nonreach
runtime (wallclock)	4.30235695839 seconds
cpu usage	15.517402821
max memory	9.28407552E8

stage attributes

key	value
output-size	29949
starexec-result	YES

output

/export/starexec/sandbox/solver/bin/starexec_run_ttt2-1.17+nonreach /export/starexec/sandbox/benchmark/theBenchmark.xml /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES Problem: U11(tt(),V2) -> U12(isNat(activate(V2))) U12(tt()) -> tt() U21(tt()) -> tt() U31(tt(),N) -> activate(N) U41(tt(),M,N) -> U42(isNat(activate(N)),activate(M),activate(N)) U42(tt(),M,N) -> s(plus(activate(N),activate(M))) isNat(n__0()) -> tt() isNat(n__plus(V1,V2)) -> U11(isNat(activate(V1)),activate(V2)) isNat(n__s(V1)) -> U21(isNat(activate(V1))) plus(N,0()) -> U31(isNat(N),N) plus(N,s(M)) -> U41(isNat(M),M,N) 0() -> n__0() plus(X1,X2) -> n__plus(X1,X2) s(X) -> n__s(X) activate(n__0()) -> 0() activate(n__plus(X1,X2)) -> plus(X1,X2) activate(n__s(X)) -> s(X) activate(X) -> X Proof: DP Processor: DPs: U11#(tt(),V2) -> activate#(V2) U11#(tt(),V2) -> isNat#(activate(V2)) U11#(tt(),V2) -> U12#(isNat(activate(V2))) U31#(tt(),N) -> activate#(N) U41#(tt(),M,N) -> activate#(M) U41#(tt(),M,N) -> activate#(N) U41#(tt(),M,N) -> isNat#(activate(N)) U41#(tt(),M,N) -> U42#(isNat(activate(N)),activate(M),activate(N)) U42#(tt(),M,N) -> activate#(M) U42#(tt(),M,N) -> activate#(N) U42#(tt(),M,N) -> plus#(activate(N),activate(M)) U42#(tt(),M,N) -> s#(plus(activate(N),activate(M))) isNat#(n__plus(V1,V2)) -> activate#(V2) isNat#(n__plus(V1,V2)) -> activate#(V1) isNat#(n__plus(V1,V2)) -> isNat#(activate(V1)) isNat#(n__plus(V1,V2)) -> U11#(isNat(activate(V1)),activate(V2)) isNat#(n__s(V1)) -> activate#(V1) isNat#(n__s(V1)) -> isNat#(activate(V1)) isNat#(n__s(V1)) -> U21#(isNat(activate(V1))) plus#(N,0()) -> isNat#(N) plus#(N,0()) -> U31#(isNat(N),N) plus#(N,s(M)) -> isNat#(M) plus#(N,s(M)) -> U41#(isNat(M),M,N) activate#(n__0()) -> 0#() activate#(n__plus(X1,X2)) -> plus#(X1,X2) activate#(n__s(X)) -> s#(X) TRS: U11(tt(),V2) -> U12(isNat(activate(V2))) U12(tt()) -> tt() U21(tt()) -> tt() U31(tt(),N) -> activate(N) U41(tt(),M,N) -> U42(isNat(activate(N)),activate(M),activate(N)) U42(tt(),M,N) -> s(plus(activate(N),activate(M))) isNat(n__0()) -> tt() isNat(n__plus(V1,V2)) -> U11(isNat(activate(V1)),activate(V2)) isNat(n__s(V1)) -> U21(isNat(activate(V1))) plus(N,0()) -> U31(isNat(N),N) plus(N,s(M)) -> U41(isNat(M),M,N) 0() -> n__0() plus(X1,X2) -> n__plus(X1,X2) s(X) -> n__s(X) activate(n__0()) -> 0() activate(n__plus(X1,X2)) -> plus(X1,X2) activate(n__s(X)) -> s(X) activate(X) -> X TDG Processor: DPs: U11#(tt(),V2) -> activate#(V2) U11#(tt(),V2) -> isNat#(activate(V2)) U11#(tt(),V2) -> U12#(isNat(activate(V2))) U31#(tt(),N) -> activate#(N) U41#(tt(),M,N) -> activate#(M) U41#(tt(),M,N) -> activate#(N) U41#(tt(),M,N) -> isNat#(activate(N)) U41#(tt(),M,N) -> U42#(isNat(activate(N)),activate(M),activate(N)) U42#(tt(),M,N) -> activate#(M) U42#(tt(),M,N) -> activate#(N) U42#(tt(),M,N) -> plus#(activate(N),activate(M)) U42#(tt(),M,N) -> s#(plus(activate(N),activate(M))) isNat#(n__plus(V1,V2)) -> activate#(V2) isNat#(n__plus(V1,V2)) -> activate#(V1) isNat#(n__plus(V1,V2)) -> isNat#(activate(V1)) isNat#(n__plus(V1,V2)) -> U11#(isNat(activate(V1)),activate(V2)) isNat#(n__s(V1)) -> activate#(V1) isNat#(n__s(V1)) -> isNat#(activate(V1)) isNat#(n__s(V1)) -> U21#(isNat(activate(V1))) plus#(N,0()) -> isNat#(N) plus#(N,0()) -> U31#(isNat(N),N) plus#(N,s(M)) -> isNat#(M) popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to TRS Stand 20472