SRS Stand 10685 pair #381717211

details

property	value
status	complete
benchmark	x02.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n013.star.cs.uiowa.edu
space	Secret_07_SRS

run statistics

property	value
solver	ttt2-1.17+nonreach
configuration	ttt2-1.17+nonreach
runtime (wallclock)	30.8790290356 seconds
cpu usage	122.092011183
max memory	1.650597888E9

stage attributes

key	value
output-size	12559
starexec-result	YES

output

/export/starexec/sandbox2/solver/bin/starexec_run_ttt2-1.17+nonreach /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files


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YES

Problem:
 a(b(x1)) -> c(d(x1))
 d(d(x1)) -> b(e(x1))
 b(x1) -> d(c(x1))
 d(x1) -> x1
 e(c(x1)) -> d(a(x1))
 a(x1) -> e(d(x1))

Proof:
 DP Processor:
  DPs:
   a#(b(x1)) -> d#(x1)
   d#(d(x1)) -> e#(x1)
   d#(d(x1)) -> b#(e(x1))
   b#(x1) -> d#(c(x1))
   e#(c(x1)) -> a#(x1)
   e#(c(x1)) -> d#(a(x1))
   a#(x1) -> d#(x1)
   a#(x1) -> e#(d(x1))
  TRS:
   a(b(x1)) -> c(d(x1))
   d(d(x1)) -> b(e(x1))
   b(x1) -> d(c(x1))
   d(x1) -> x1
   e(c(x1)) -> d(a(x1))
   a(x1) -> e(d(x1))
  TDG Processor:
   DPs:
    a#(b(x1)) -> d#(x1)
    d#(d(x1)) -> e#(x1)
    d#(d(x1)) -> b#(e(x1))
    b#(x1) -> d#(c(x1))
    e#(c(x1)) -> a#(x1)
    e#(c(x1)) -> d#(a(x1))
    a#(x1) -> d#(x1)
    a#(x1) -> e#(d(x1))
   TRS:
    a(b(x1)) -> c(d(x1))
    d(d(x1)) -> b(e(x1))
    b(x1) -> d(c(x1))
    d(x1) -> x1
    e(c(x1)) -> d(a(x1))
    a(x1) -> e(d(x1))
   graph:
    b#(x1) -> d#(c(x1)) -> d#(d(x1)) -> b#(e(x1))
    b#(x1) -> d#(c(x1)) -> d#(d(x1)) -> e#(x1)
    e#(c(x1)) -> d#(a(x1)) -> d#(d(x1)) -> b#(e(x1))
    e#(c(x1)) -> d#(a(x1)) -> d#(d(x1)) -> e#(x1)
    e#(c(x1)) -> a#(x1) -> a#(x1) -> e#(d(x1))
    e#(c(x1)) -> a#(x1) -> a#(x1) -> d#(x1)
    e#(c(x1)) -> a#(x1) -> a#(b(x1)) -> d#(x1)
    d#(d(x1)) -> b#(e(x1)) -> b#(x1) -> d#(c(x1))
    d#(d(x1)) -> e#(x1) -> e#(c(x1)) -> d#(a(x1))
    d#(d(x1)) -> e#(x1) -> e#(c(x1)) -> a#(x1)
    a#(b(x1)) -> d#(x1) -> d#(d(x1)) -> b#(e(x1))
    a#(b(x1)) -> d#(x1) -> d#(d(x1)) -> e#(x1)
    a#(x1) -> e#(d(x1)) -> e#(c(x1)) -> d#(a(x1))
    a#(x1) -> e#(d(x1)) -> e#(c(x1)) -> a#(x1)
    a#(x1) -> d#(x1) -> d#(d(x1)) -> b#(e(x1))
    a#(x1) -> d#(x1) -> d#(d(x1)) -> e#(x1)
   EDG Processor:
    DPs:
     a#(b(x1)) -> d#(x1)
     d#(d(x1)) -> e#(x1)
     d#(d(x1)) -> b#(e(x1))
     b#(x1) -> d#(c(x1))
     e#(c(x1)) -> a#(x1)
     e#(c(x1)) -> d#(a(x1))
     a#(x1) -> d#(x1)
     a#(x1) -> e#(d(x1))
    TRS:
     a(b(x1)) -> c(d(x1))
     d(d(x1)) -> b(e(x1))
     b(x1) -> d(c(x1))
     d(x1) -> x1
     e(c(x1)) -> d(a(x1))
     a(x1) -> e(d(x1))
    graph:
     e#(c(x1)) -> d#(a(x1)) -> d#(d(x1)) -> e#(x1)
     e#(c(x1)) -> d#(a(x1)) -> d#(d(x1)) -> b#(e(x1))
     e#(c(x1)) -> a#(x1) -> a#(b(x1)) -> d#(x1)
     e#(c(x1)) -> a#(x1) -> a#(x1) -> d#(x1)
     e#(c(x1)) -> a#(x1) -> a#(x1) -> e#(d(x1))
     d#(d(x1)) -> b#(e(x1)) -> b#(x1) -> d#(c(x1))
     d#(d(x1)) -> e#(x1) -> e#(c(x1)) -> a#(x1)
     d#(d(x1)) -> e#(x1) -> e#(c(x1)) -> d#(a(x1))
     a#(b(x1)) -> d#(x1) -> d#(d(x1)) -> e#(x1)
     a#(b(x1)) -> d#(x1) -> d#(d(x1)) -> b#(e(x1))
     a#(x1) -> e#(d(x1)) -> e#(c(x1)) -> a#(x1)
     a#(x1) -> e#(d(x1)) -> e#(c(x1)) -> d#(a(x1))
     a#(x1) -> d#(x1) -> d#(d(x1)) -> e#(x1)
     a#(x1) -> d#(x1) -> d#(d(x1)) -> b#(e(x1))

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job log

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actions all output return to SRS Stand 10685