details

property	value
status	complete
benchmark	15.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n046.star.cs.uiowa.edu
space	Bouchare_06

run statistics

property	value
solver	ttt2-1.17+nonreach
configuration	ttt2-1.17+nonreach
runtime (wallclock)	11.1440000534 seconds
cpu usage	42.701380941
max memory	6.74967552E8

stage attributes

key	value
output-size	48387
starexec-result	YES

output

/export/starexec/sandbox2/solver/bin/starexec_run_ttt2-1.17+nonreach /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES Problem: a(b(a(x1))) -> b(x1) b(a(b(x1))) -> b(b(b(x1))) b(b(x1)) -> a(a(a(x1))) Proof: DP Processor: DPs: a#(b(a(x1))) -> b#(x1) b#(a(b(x1))) -> b#(b(x1)) b#(a(b(x1))) -> b#(b(b(x1))) b#(b(x1)) -> a#(x1) b#(b(x1)) -> a#(a(x1)) b#(b(x1)) -> a#(a(a(x1))) TRS: a(b(a(x1))) -> b(x1) b(a(b(x1))) -> b(b(b(x1))) b(b(x1)) -> a(a(a(x1))) TDG Processor: DPs: a#(b(a(x1))) -> b#(x1) b#(a(b(x1))) -> b#(b(x1)) b#(a(b(x1))) -> b#(b(b(x1))) b#(b(x1)) -> a#(x1) b#(b(x1)) -> a#(a(x1)) b#(b(x1)) -> a#(a(a(x1))) TRS: a(b(a(x1))) -> b(x1) b(a(b(x1))) -> b(b(b(x1))) b(b(x1)) -> a(a(a(x1))) graph: b#(b(x1)) -> a#(a(a(x1))) -> a#(b(a(x1))) -> b#(x1) b#(b(x1)) -> a#(a(x1)) -> a#(b(a(x1))) -> b#(x1) b#(b(x1)) -> a#(x1) -> a#(b(a(x1))) -> b#(x1) b#(a(b(x1))) -> b#(b(b(x1))) -> b#(b(x1)) -> a#(a(a(x1))) b#(a(b(x1))) -> b#(b(b(x1))) -> b#(b(x1)) -> a#(a(x1)) b#(a(b(x1))) -> b#(b(b(x1))) -> b#(b(x1)) -> a#(x1) b#(a(b(x1))) -> b#(b(b(x1))) -> b#(a(b(x1))) -> b#(b(b(x1))) b#(a(b(x1))) -> b#(b(b(x1))) -> b#(a(b(x1))) -> b#(b(x1)) b#(a(b(x1))) -> b#(b(x1)) -> b#(b(x1)) -> a#(a(a(x1))) b#(a(b(x1))) -> b#(b(x1)) -> b#(b(x1)) -> a#(a(x1)) b#(a(b(x1))) -> b#(b(x1)) -> b#(b(x1)) -> a#(x1) b#(a(b(x1))) -> b#(b(x1)) -> b#(a(b(x1))) -> b#(b(b(x1))) b#(a(b(x1))) -> b#(b(x1)) -> b#(a(b(x1))) -> b#(b(x1)) a#(b(a(x1))) -> b#(x1) -> b#(b(x1)) -> a#(a(a(x1))) a#(b(a(x1))) -> b#(x1) -> b#(b(x1)) -> a#(a(x1)) a#(b(a(x1))) -> b#(x1) -> b#(b(x1)) -> a#(x1) a#(b(a(x1))) -> b#(x1) -> b#(a(b(x1))) -> b#(b(b(x1))) a#(b(a(x1))) -> b#(x1) -> b#(a(b(x1))) -> b#(b(x1)) Root-Labeling Processor: DPs: a{#,(f4)}(f4(b)(b(a)(a(f4)(x1)))) -> b{#,(f4)}(f4(f4)(x1)) a{#,(f4)}(f4(b)(b(a)(a(a)(x1)))) -> b{#,(f4)}(f4(a)(x1)) a{#,(f4)}(f4(b)(b(a)(a(b)(x1)))) -> b{#,(f4)}(f4(b)(x1)) b{#,(f4)}(f4(a)(a(b)(b(f4)(x1)))) -> b{#,(f4)}(f4(b)(b(f4)(x1))) b{#,(f4)}(f4(a)(a(b)(b(a)(x1)))) -> b{#,(f4)}(f4(b)(b(a)(x1))) b{#,(f4)}(f4(a)(a(b)(b(b)(x1)))) -> b{#,(f4)}(f4(b)(b(b)(x1))) b{#,(f4)}(f4(a)(a(b)(b(f4)(x1)))) -> b{#,(f4)}(f4(b)(b(b)(b(f4)(x1)))) b{#,(f4)}(f4(a)(a(b)(b(a)(x1)))) -> b{#,(f4)}(f4(b)(b(b)(b(a)(x1)))) b{#,(f4)}(f4(a)(a(b)(b(b)(x1)))) -> b{#,(f4)}(f4(b)(b(b)(b(b)(x1)))) b{#,(f4)}(f4(b)(b(f4)(x1))) -> a{#,(f4)}(f4(f4)(x1)) b{#,(f4)}(f4(b)(b(a)(x1))) -> a{#,(f4)}(f4(a)(x1)) b{#,(f4)}(f4(b)(b(b)(x1))) -> a{#,(f4)}(f4(b)(x1)) b{#,(f4)}(f4(b)(b(f4)(x1))) -> a{#,(f4)}(f4(a)(a(f4)(x1))) b{#,(f4)}(f4(b)(b(a)(x1))) -> a{#,(f4)}(f4(a)(a(a)(x1))) b{#,(f4)}(f4(b)(b(b)(x1))) -> a{#,(f4)}(f4(a)(a(b)(x1))) b{#,(f4)}(f4(b)(b(f4)(x1))) -> a{#,(f4)}(f4(a)(a(a)(a(f4)(x1)))) b{#,(f4)}(f4(b)(b(a)(x1))) -> a{#,(f4)}(f4(a)(a(a)(a(a)(x1)))) b{#,(f4)}(f4(b)(b(b)(x1))) -> a{#,(f4)}(f4(a)(a(a)(a(b)(x1)))) TRS: f4(a)(a(b)(b(a)(a(f4)(x1)))) -> f4(b)(b(f4)(x1)) f4(a)(a(b)(b(a)(a(a)(x1)))) -> f4(b)(b(a)(x1)) f4(a)(a(b)(b(a)(a(b)(x1)))) -> f4(b)(b(b)(x1)) a(a)(a(b)(b(a)(a(f4)(x1)))) -> a(b)(b(f4)(x1)) a(a)(a(b)(b(a)(a(a)(x1)))) -> a(b)(b(a)(x1)) a(a)(a(b)(b(a)(a(b)(x1)))) -> a(b)(b(b)(x1)) b(a)(a(b)(b(a)(a(f4)(x1)))) -> b(b)(b(f4)(x1)) b(a)(a(b)(b(a)(a(a)(x1)))) -> b(b)(b(a)(x1)) b(a)(a(b)(b(a)(a(b)(x1)))) -> b(b)(b(b)(x1)) b(a)(a(b)(b(f4)(x1))) -> b(b)(b(b)(b(f4)(x1))) b(a)(a(b)(b(a)(x1))) -> b(b)(b(b)(b(a)(x1))) b(a)(a(b)(b(b)(x1))) -> b(b)(b(b)(b(b)(x1))) f4(b)(b(b)(b(f4)(x1))) -> f4(a)(a(a)(a(a)(a(f4)(x1)))) f4(b)(b(b)(b(a)(x1))) -> f4(a)(a(a)(a(a)(a(a)(x1)))) f4(b)(b(b)(b(b)(x1))) -> f4(a)(a(a)(a(a)(a(b)(x1)))) a(b)(b(b)(b(f4)(x1))) -> a(a)(a(a)(a(a)(a(f4)(x1)))) a(b)(b(b)(b(a)(x1))) -> a(a)(a(a)(a(a)(a(a)(x1)))) a(b)(b(b)(b(b)(x1))) -> a(a)(a(a)(a(a)(a(b)(x1)))) b(b)(b(b)(b(f4)(x1))) -> b(a)(a(a)(a(a)(a(f4)(x1)))) b(b)(b(b)(b(a)(x1))) -> b(a)(a(a)(a(a)(a(a)(x1)))) b(b)(b(b)(b(b)(x1))) -> b(a)(a(a)(a(a)(a(b)(x1)))) TDG Processor: popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to SRS Stand 10685