details

property	value
status	complete
benchmark	MYNAT_nokinds.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n033.star.cs.uiowa.edu
space	Maude_06

run statistics

property	value
solver	muterm 5.18
configuration	default
runtime (wallclock)	1.5701110363 seconds
cpu usage	1.402403562
max memory	1.1087872E7

stage attributes

key	value
output-size	11346
starexec-result	YES

output

/export/starexec/sandbox2/solver/bin/starexec_run_default /export/starexec/sandbox2/benchmark/theBenchmark.xml /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES Problem 1: (VAR M N V1 V2 X) (STRATEGY CONTEXTSENSITIVE (U11 1) (U21 1) (U31 1) (U41 1) (and 1) (isNat) (plus 1 2) (x 1 2) (0) (s 1) (tt) ) (RULES U11(tt,N) -> N U21(tt,M,N) -> s(plus(N,M)) U31(tt) -> 0 U41(tt,M,N) -> plus(x(N,M),N) and(tt,X) -> X isNat(plus(V1,V2)) -> and(isNat(V1),isNat(V2)) isNat(x(V1,V2)) -> and(isNat(V1),isNat(V2)) isNat(0) -> tt isNat(s(V1)) -> isNat(V1) plus(N,0) -> U11(isNat(N),N) plus(N,s(M)) -> U21(and(isNat(M),isNat(N)),M,N) x(N,0) -> U31(isNat(N)) x(N,s(M)) -> U41(and(isNat(M),isNat(N)),M,N) ) Problem 1: Dependency Pairs Processor: -> Pairs: U11#(tt,N) -> N U21#(tt,M,N) -> PLUS(N,M) U21#(tt,M,N) -> M U21#(tt,M,N) -> N U41#(tt,M,N) -> PLUS(x(N,M),N) U41#(tt,M,N) -> X(N,M) U41#(tt,M,N) -> M U41#(tt,M,N) -> N AND(tt,X) -> X ISNAT(plus(V1,V2)) -> AND(isNat(V1),isNat(V2)) ISNAT(plus(V1,V2)) -> ISNAT(V1) ISNAT(x(V1,V2)) -> AND(isNat(V1),isNat(V2)) ISNAT(x(V1,V2)) -> ISNAT(V1) ISNAT(s(V1)) -> ISNAT(V1) PLUS(N,0) -> U11#(isNat(N),N) PLUS(N,0) -> ISNAT(N) PLUS(N,s(M)) -> U21#(and(isNat(M),isNat(N)),M,N) PLUS(N,s(M)) -> AND(isNat(M),isNat(N)) PLUS(N,s(M)) -> ISNAT(M) X(N,0) -> U31#(isNat(N)) X(N,0) -> ISNAT(N) X(N,s(M)) -> U41#(and(isNat(M),isNat(N)),M,N) X(N,s(M)) -> AND(isNat(M),isNat(N)) X(N,s(M)) -> ISNAT(M) -> Rules: U11(tt,N) -> N U21(tt,M,N) -> s(plus(N,M)) U31(tt) -> 0 U41(tt,M,N) -> plus(x(N,M),N) and(tt,X) -> X isNat(plus(V1,V2)) -> and(isNat(V1),isNat(V2)) isNat(x(V1,V2)) -> and(isNat(V1),isNat(V2)) isNat(0) -> tt isNat(s(V1)) -> isNat(V1) plus(N,0) -> U11(isNat(N),N) plus(N,s(M)) -> U21(and(isNat(M),isNat(N)),M,N) x(N,0) -> U31(isNat(N)) x(N,s(M)) -> U41(and(isNat(M),isNat(N)),M,N) -> Unhiding Rules: isNat(N) -> ISNAT(N) isNat(V2) -> ISNAT(V2) Problem 1: SCC Processor: -> Pairs: U11#(tt,N) -> N U21#(tt,M,N) -> PLUS(N,M) U21#(tt,M,N) -> M U21#(tt,M,N) -> N U41#(tt,M,N) -> PLUS(x(N,M),N) U41#(tt,M,N) -> X(N,M) U41#(tt,M,N) -> M U41#(tt,M,N) -> N AND(tt,X) -> X ISNAT(plus(V1,V2)) -> AND(isNat(V1),isNat(V2)) popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to TRS Conte Sensi 17651