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Integ Trans Syste 27634 pair #381736977
details
property
value
status
complete
benchmark
ex33.t2.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n002.star.cs.uiowa.edu
space
From_T2
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp17
runtime (wallclock)
0.0245308876038 seconds
cpu usage
0.020905933
max memory
3833856.0
stage attributes
key
value
output-size
2689
starexec-result
YES
output
/export/starexec/sandbox2/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox2/benchmark/theBenchmark.smt2 /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l6, true> <l1, l2, true> <l3, l1, (undef11 = undef11), par{tmp___0^0 -> undef11}> <l4, l1, ((0 + tmp___1^0) <= ~(1)) /\ (~(1) <= (0 + tmp___1^0)) /\ (undef13 = undef13) /\ (undef15 = undef15), par{__len9^0 -> undef13, __val8^0 -> 0, tmp10^0 -> undef15}> <l4, l3, (0 <= (0 + tmp___1^0))> <l4, l3, ((1 + tmp___1^0) <= ~(1))> <l5, l4, (undef34 = undef34) /\ (undef36 = undef36), par{tmp^0 -> undef34, tmp___1^0 -> undef36}> <l6, l5, true> Fresh variables: undef11, undef13, undef15, undef34, undef36, Undef variables: undef11, undef13, undef15, undef34, undef36, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l2, (undef34 = undef34) /\ (undef36 = undef36) /\ ((0 + undef36) <= ~(1)) /\ (~(1) <= (0 + undef36)) /\ (undef13 = undef13) /\ (undef15 = undef15)> <l0, l2, (undef34 = undef34) /\ (undef36 = undef36) /\ (0 <= (0 + undef36)) /\ (undef11 = undef11)> <l0, l2, (undef34 = undef34) /\ (undef36 = undef36) /\ ((1 + undef36) <= ~(1)) /\ (undef11 = undef11)> Fresh variables: undef11, undef13, undef15, undef34, undef36, Undef variables: undef11, undef13, undef15, undef34, undef36, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: Variables: Precedence: Graph 0 Graph 1 <l0, l2, 1 + undef36 = 0, {all remain the same}> <l0, l2, 0 <= undef36, {all remain the same}> <l0, l2, 2 + undef36 <= 0, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Analyzing SCC {l2}... No cycles found. �[32mProgram Terminates�[0m
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