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Integ Trans Syste 27634 pair #381737050
details
property
value
status
complete
benchmark
IntRTA.jar-obl-8.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n037.star.cs.uiowa.edu
space
From_AProVE_2014
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp17
runtime (wallclock)
0.0355060100555 seconds
cpu usage
0.031091657
max memory
4517888.0
stage attributes
key
value
output-size
3521
starexec-result
YES
output
/export/starexec/sandbox/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox/benchmark/theBenchmark.smt2 /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l3, true> <l1, l2, (undef3 > ~(1)) /\ (arg2 > ~(1)) /\ (undef4 > ~(1)) /\ (arg1 > 0) /\ (undef1 > 0) /\ (undef2 > 0), par{arg1 -> undef1, arg2 -> undef2, arg3 -> undef3, arg4 -> undef4}> <l2, l2, (arg4 > ~(1)) /\ (arg3 > arg4) /\ (arg1 >= undef5) /\ (arg2 >= (undef6 - 1)) /\ (arg1 > 0) /\ (arg2 > 0) /\ (undef5 > 0) /\ (undef6 > 0) /\ ((arg3 + 2) <= arg1) /\ ((arg4 + 2) <= arg2), par{arg1 -> undef5, arg2 -> undef6, arg4 -> (arg4 + 1)}> <l3, l1, true, par{arg1 -> undef9, arg2 -> undef10, arg3 -> undef11, arg4 -> undef12}> Fresh variables: undef1, undef2, undef3, undef4, undef5, undef6, undef9, undef10, undef11, undef12, Undef variables: undef1, undef2, undef3, undef4, undef5, undef6, undef9, undef10, undef11, undef12, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l2, (arg1 = undef1) /\ (arg2 = undef2) /\ (arg3 = undef3) /\ (arg4 = undef4) /\ (undef3 > ~(1)) /\ (undef10 > ~(1)) /\ (undef4 > ~(1)) /\ (undef9 > 0) /\ (undef1 > 0) /\ (undef2 > 0)> <l2, l2, (arg4 > ~(1)) /\ (arg3 > arg4) /\ (arg1 >= undef5) /\ (arg2 >= (undef6 - 1)) /\ (arg1 > 0) /\ (arg2 > 0) /\ (undef5 > 0) /\ (undef6 > 0) /\ ((arg3 + 2) <= arg1) /\ ((arg4 + 2) <= arg2), par{arg1 -> undef5, arg2 -> undef6, arg4 -> (arg4 + 1)}> Fresh variables: undef1, undef2, undef3, undef4, undef5, undef6, undef9, undef10, undef11, undef12, Undef variables: undef1, undef2, undef3, undef4, undef5, undef6, undef9, undef10, undef11, undef12, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l2, l2, 1 <= arg1 /\ 1 <= arg2 /\ 1 + arg4 <= arg3 /\ 1 <= undef5 /\ 1 <= undef6 /\ undef6 <= 1 + arg2 /\ undef5 <= arg1 /\ 0 <= arg4 /\ 2 + arg3 <= arg1 /\ 2 + arg4 <= arg2, {arg1 -> undef5, arg2 -> undef6, arg4 -> 1 + arg4, rest remain the same}> Variables: arg1, arg2, arg3, arg4 Precedence: Graph 0 Graph 1 <l0, l2, 1 <= undef1 /\ 1 <= undef2 /\ 1 <= undef9 /\ 0 <= undef3 /\ 0 <= undef4 /\ 0 <= undef10 /\ arg1 = undef1 /\ arg2 = undef2 /\ arg3 = undef3 /\ arg4 = undef4, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.004535 Checking conditional termination of SCC {l2}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.001683s �[33mRanking function: �[36m-1 + arg3 - arg4�[0m New Graphs: �[32mProgram Terminates�[0m
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