details

property	value
status	complete
benchmark	DivWithoutMinus.jar-obl-8.smt2
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n023.star.cs.uiowa.edu
space	From_AProVE_2014

run statistics

property	value
solver	VeryMax-termCOMP17
configuration	termcomp17
runtime (wallclock)	0.0416359901428 seconds
cpu usage	0.037880149
max memory	5537792.0

stage attributes

key	value
output-size	3512
starexec-result	YES

output

/export/starexec/sandbox2/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox2/benchmark/theBenchmark.smt2 /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l3, true> <l1, l2, (undef2 > ~(1)) /\ (arg2 > ~(1)) /\ (undef1 > ~(1)) /\ (arg1 > 0), par{arg1 -> undef1, arg2 -> undef2, arg3 -> undef2, arg4 -> undef2}> <l2, l2, (arg3 > 0) /\ (0 = arg2) /\ (arg3 = arg4), par{arg2 -> arg3, arg4 -> arg3}> <l2, l2, (arg1 > 0) /\ (arg3 > 0) /\ (arg2 > 0) /\ (arg3 = arg4), par{arg1 -> (arg1 - 1), arg2 -> (arg2 - 1), arg4 -> arg3}> <l3, l1, true, par{arg1 -> undef13, arg2 -> undef14, arg3 -> undef15, arg4 -> undef16}> Fresh variables: undef1, undef2, undef13, undef14, undef15, undef16, Undef variables: undef1, undef2, undef13, undef14, undef15, undef16, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l2, (arg1 = undef1) /\ (arg2 = undef2) /\ (arg3 = undef2) /\ (arg4 = undef2) /\ (undef2 > ~(1)) /\ (undef14 > ~(1)) /\ (undef1 > ~(1)) /\ (undef13 > 0)> <l2, l2, (arg3 > 0) /\ (0 = arg2) /\ (arg3 = arg4), par{arg2 -> arg3, arg4 -> arg3}> <l2, l2, (arg1 > 0) /\ (arg3 > 0) /\ (arg2 > 0) /\ (arg3 = arg4), par{arg1 -> (arg1 - 1), arg2 -> (arg2 - 1), arg4 -> arg3}> Fresh variables: undef1, undef2, undef13, undef14, undef15, undef16, Undef variables: undef1, undef2, undef13, undef14, undef15, undef16, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l2, l2, 1 <= arg3 /\ arg2 = 0 /\ arg3 = arg4, {arg2 -> arg3, arg4 -> arg3, rest remain the same}> <l2, l2, 1 <= arg1 /\ 1 <= arg2 /\ 1 <= arg3 /\ arg3 = arg4, {arg1 -> -1 + arg1, arg2 -> -1 + arg2, arg4 -> arg3, rest remain the same}> Variables: arg2, arg3, arg4, arg1 Precedence: Graph 0 Graph 1 <l0, l2, 1 <= undef13 /\ 0 <= undef1 /\ 0 <= undef2 /\ 0 <= undef14 /\ arg1 = undef1 /\ arg2 = undef2 /\ arg3 = undef2 /\ arg4 = undef2, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.010114 Checking conditional termination of SCC {l2}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.001765s �[33mRanking function: �[36marg1�[0m New Graphs: Transitions: <l2, l2, 1 <= arg3 /\ arg2 = 0 /\ arg3 = arg4, {arg2 -> arg3, arg4 -> arg3, rest remain the same}> popout

output may be truncated. 'popout' for the full output.

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all output return to Integ Trans Syste 27634