details

property	value
status	complete
benchmark	simple_pre1.t2.smt2
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n098.star.cs.uiowa.edu
space	From_T2

run statistics

property	value
solver	VeryMax-termCOMP17
configuration	termcomp17
runtime (wallclock)	0.0239160060883 seconds
cpu usage	0.019299604
max memory	3833856.0

stage attributes

key	value
output-size	2004
starexec-result	YES

output

/export/starexec/sandbox2/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox2/benchmark/theBenchmark.smt2 /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l3, true> <l1, l2, (undef4 = ~(1)) /\ (undef3 = (0 + undef4)) /\ (undef2 = (0 + undef3)), par{a^0 -> (0 + undef2), ret_incr3^0 -> undef2, x2^0 -> undef3}> <l3, l1, true> Fresh variables: undef2, undef3, undef4, Undef variables: undef2, undef3, undef4, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l2, (undef4 = ~(1)) /\ (undef3 = (0 + undef4)) /\ (undef2 = (0 + undef3))> Fresh variables: undef2, undef3, undef4, Undef variables: undef2, undef3, undef4, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: Variables: Precedence: Graph 0 Graph 1 <l0, l2, 1 + undef4 = 0 /\ undef2 = undef3 /\ undef3 = undef4, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Analyzing SCC {l2}... No cycles found. �[32mProgram Terminates�[0m popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to Integ Trans Syste 27634