details

property	value
status	complete
benchmark	armc-difficult_defect.t2.smt2
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n103.star.cs.uiowa.edu
space	From_T2

run statistics

property	value
solver	VeryMax-termCOMP17
configuration	termcomp17
runtime (wallclock)	0.0436248779297 seconds
cpu usage	0.074925267
max memory	1.4749696E7

stage attributes

key	value
output-size	2973
starexec-result	YES

output

/export/starexec/sandbox2/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox2/benchmark/theBenchmark.smt2 /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l4, true> <l1, l2, ((1 + p^0) <= (0 + c^0)), par{p^0 -> (0 + s^0), s^0 -> (1 + s^0)}> <l2, l1, true> <l3, l1, true, par{p^0 -> 1, s^0 -> 1}> <l4, l3, true> Fresh variables: Undef variables: Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l1, (p^0 = 1) /\ (s^0 = 1)> <l1, l1, ((1 + p^0) <= (0 + c^0)), par{p^0 -> (0 + s^0), s^0 -> (1 + s^0)}> Fresh variables: Undef variables: Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l1, l1, 1 + p^0 <= c^0, {p^0 -> s^0, s^0 -> 1 + s^0, rest remain the same}> Variables: c^0, p^0, s^0 Precedence: Graph 0 Graph 1 <l0, l1, p^0 = 1 /\ s^0 = 1, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 1 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.002351 Checking conditional termination of SCC {l1}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.000655s LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.001783s [27113 : 27114] [27113 : 27115] Successful child: 27114 [ Invariant Graph ] �[33mStrengthening and disabling transitions...�[0m popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to Integ Trans Syste 27634