details

property	value
status	complete
benchmark	small29.t2.smt2
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n081.star.cs.uiowa.edu
space	From_T2

run statistics

property	value
solver	VeryMax-termCOMP17
configuration	termcomp17
runtime (wallclock)	4.18530607224 seconds
cpu usage	5.322392479
max memory	4.849664E7

stage attributes

key	value
output-size	3191
starexec-result	NO

output

/export/starexec/sandbox/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox/benchmark/theBenchmark.smt2 /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- NO Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l4, true> <l1, l2, ((0 + x^0) <= (0 + y^0)) /\ ((0 + y^0) <= (0 + x^0)), par{x^0 -> (0 + x^0)}> <l2, l1, true> <l3, l1, true> <l4, l3, true> Fresh variables: Undef variables: Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l1, true> <l1, l1, ((0 + x^0) <= (0 + y^0)) /\ ((0 + y^0) <= (0 + x^0)), par{x^0 -> (0 + x^0)}> Fresh variables: Undef variables: Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l1, l1, x^0 = y^0, {all remain the same}> Variables: x^0, y^0 Precedence: Graph 0 Graph 1 <l0, l1, true, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 1 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.001755 > No variable changes in termination graph. Checking conditional unfeasibility... Calling Safety with literal 1 + x^0 <= y^0 and entry <l1, l1, x^0 <= y^0, {all remain the same}> LOG: CALL check - Post:1 + x^0 <= y^0 - Process 1 * Exit transition: <l1, l1, x^0 <= y^0, {all remain the same}> * Postcondition : 1 + x^0 <= y^0 Postcodition moved up: 1 + x^0 <= y^0 LOG: Try proving POST LOG: CALL check - Post:1 + x^0 <= y^0 - Process 2 * Exit transition: <l0, l1, x^0 <= y^0, {all remain the same}> * Postcondition : 1 + x^0 <= y^0 popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to Integ Trans Syste 27634