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Integ Trans Syste 27634 pair #381737265
details
property
value
status
complete
benchmark
byron-2.t2.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n056.star.cs.uiowa.edu
space
From_T2
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp17
runtime (wallclock)
0.0374858379364 seconds
cpu usage
0.033690633
max memory
5009408.0
stage attributes
key
value
output-size
4352
starexec-result
YES
output
/export/starexec/sandbox2/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox2/benchmark/theBenchmark.smt2 /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l8, true> <l1, l2, true> <l2, l3, ((0 + x_13^0) <= 0), par{rt_11^0 -> (0 + st_14^0)}> <l2, l4, (1 <= (0 + x_13^0)) /\ (undef25 = undef25) /\ (undef20 = (0 + undef25)) /\ (undef18 = undef18) /\ (0 <= (0 + undef20)) /\ ((0 + undef20) <= 0) /\ (undef24 = (~(1) + y_17^0)) /\ (undef22 = undef22) /\ (2 <= (0 + undef24)), par{nd_12^0 -> undef18, rv_15^0 -> undef20, st_16^0 -> undef22, y_17^0 -> undef24}> <l4, l2, true> <l2, l5, (1 <= (0 + x_13^0)) /\ (undef42 = undef42) /\ (undef35 = undef35), par{nd_12^0 -> undef35, rv_15^0 -> (0 + undef42)}> <l5, l6, (undef43 = __disjvr_0^0) /\ (__disjvr_0^0 = undef43), par{__disjvr_0^0 -> undef43}> <l6, l7, (undef59 = undef59) /\ (undef52 = undef52), par{nd_12^0 -> undef52, x_13^0 -> (~(1) + x_13^0), y_17^0 -> (0 + undef59)}> <l7, l2, true> <l8, l1, true> Fresh variables: undef18, undef20, undef22, undef24, undef25, undef35, undef42, undef43, undef52, undef59, Undef variables: undef18, undef20, undef22, undef24, undef25, undef35, undef42, undef43, undef52, undef59, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l2, true> <l2, l3, ((0 + x_13^0) <= 0)> <l2, l2, (1 <= (0 + x_13^0)) /\ (undef25 = undef25) /\ (undef20 = (0 + undef25)) /\ (undef18 = undef18) /\ (0 <= (0 + undef20)) /\ ((0 + undef20) <= 0) /\ (undef24 = (~(1) + y_17^0)) /\ (undef22 = undef22) /\ (2 <= (0 + undef24)), par{y_17^0 -> undef24}> <l2, l2, (1 <= (0 + x_13^0)) /\ (undef42 = undef42) /\ (undef35 = undef35) /\ (undef43 = __disjvr_0^0) /\ (__disjvr_0^0 = undef43) /\ (undef59 = undef59) /\ (undef52 = undef52), par{__disjvr_0^0 -> undef43, x_13^0 -> (~(1) + x_13^0), y_17^0 -> (0 + undef59)}> Fresh variables: undef18, undef20, undef22, undef24, undef25, undef35, undef42, undef43, undef52, undef59, Undef variables: undef18, undef20, undef22, undef24, undef25, undef35, undef42, undef43, undef52, undef59, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l2, l2, 1 <= x_13^0 /\ 2 <= undef24 /\ undef20 = 0 /\ undef20 = undef25 /\ y_17^0 = 1 + undef24, {y_17^0 -> undef24, rest remain the same}> <l2, l2, 1 <= x_13^0 /\ __disjvr_0^0 = undef43, {__disjvr_0^0 -> undef43, x_13^0 -> -1 + x_13^0, y_17^0 -> undef59, rest remain the same}> Variables: x_13^0, y_17^0, __disjvr_0^0 Graph 2: Transitions: Variables: Precedence: Graph 0 Graph 1 <l0, l2, true, {all remain the same}> Graph 2 <l2, l3, x_13^0 <= 0, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 1 ) ( 3 , 2 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** *******************************************************************************************
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