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Integ Trans Syste 27634 pair #381737283
details
property
value
status
complete
benchmark
bitcount32.t2_fixed.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n110.star.cs.uiowa.edu
space
From_T2
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp17
runtime (wallclock)
0.0332460403442 seconds
cpu usage
0.029546896
max memory
4644864.0
stage attributes
key
value
output-size
3703
starexec-result
YES
output
/export/starexec/sandbox/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox/benchmark/theBenchmark.smt2 /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l7, true> <l1, l2, true, par{nI6^0 -> (1 + nI6^0), res5^0 -> ((0 + res5^0) + tmp7^0)}> <l3, l1, true, par{tmp7^0 -> 0}> <l3, l1, true, par{tmp7^0 -> 1}> <l4, l5, (32 <= (0 + nI6^0)) /\ (undef40 = (0 + res5^0)) /\ (undef36 = (0 + nX^0)) /\ (undef45 = (0 + undef36)) /\ (undef46 = undef46) /\ (undef47 = undef47) /\ (undef48 = undef48) /\ (undef49 = undef49) /\ (undef38 = undef38) /\ (undef41 = (0 + undef38)), par{nX9^0 -> undef36, res10^0 -> undef38, ret_nBC18^0 -> undef40, ret_nBC211^0 -> undef41, tmp^0 -> (0 + undef40), tmp___0^0 -> (0 + undef41)}> <l4, l3, ((1 + nI6^0) <= 32)> <l2, l4, true> <l6, l2, true, par{nI6^0 -> 0, nX4^0 -> (0 + nX^0), res5^0 -> 0}> <l7, l6, true> Fresh variables: undef36, undef38, undef40, undef41, undef45, undef46, undef47, undef48, undef49, Undef variables: undef36, undef38, undef40, undef41, undef45, undef46, undef47, undef48, undef49, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l2, (nI6^0 = 0) /\ (res5^0 = 0)> <l2, l5, (32 <= (0 + nI6^0)) /\ (undef40 = (0 + res5^0)) /\ (undef36 = (0 + nX^0)) /\ (undef45 = (0 + undef36)) /\ (undef46 = undef46) /\ (undef47 = undef47) /\ (undef48 = undef48) /\ (undef49 = undef49) /\ (undef38 = undef38) /\ (undef41 = (0 + undef38))> <l2, l2, ((1 + nI6^0) <= 32), par{nI6^0 -> (1 + nI6^0), res5^0 -> ((0 + res5^0) + 0)}> <l2, l2, ((1 + nI6^0) <= 32), par{nI6^0 -> (1 + nI6^0), res5^0 -> ((0 + res5^0) + 1)}> Fresh variables: undef36, undef38, undef40, undef41, undef45, undef46, undef47, undef48, undef49, Undef variables: undef36, undef38, undef40, undef41, undef45, undef46, undef47, undef48, undef49, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l2, l2, nI6^0 <= 31, {nI6^0 -> 1 + nI6^0, rest remain the same}> <l2, l2, nI6^0 <= 31, {nI6^0 -> 1 + nI6^0, res5^0 -> 1 + res5^0, rest remain the same}> Variables: nI6^0, res5^0 Graph 2: Transitions: Variables: Precedence: Graph 0 Graph 1 <l0, l2, nI6^0 = 0 /\ res5^0 = 0, {all remain the same}> Graph 2 <l2, l5, 32 <= nI6^0 /\ nX^0 = undef36 /\ res5^0 = undef40 /\ undef36 = undef45 /\ undef38 = undef41, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 1 ) ( 5 , 2 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0
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