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Integ Trans Syste 27634 pair #381737284
details
property
value
status
complete
benchmark
LoopingNonterm.jar-obl-8.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n073.star.cs.uiowa.edu
space
From_AProVE_2014
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp17
runtime (wallclock)
5.24165797234 seconds
cpu usage
9.16159516
max memory
6.43063808E8
stage attributes
key
value
output-size
7037
starexec-result
NO
output
/export/starexec/sandbox2/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox2/benchmark/theBenchmark.smt2 /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- NO Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l3, true> <l1, l2, (undef1 <= arg1) /\ (arg2 > ~(1)) /\ (arg1 > 0) /\ (undef1 > 0), par{arg1 -> undef1, arg2 -> 0, arg3 -> arg2}> <l2, l2, (undef7 > ~(1)) /\ (arg3 > arg2) /\ (arg2 > ~(1)) /\ (undef4 <= arg1) /\ (arg1 > 0) /\ (undef4 > 0), par{arg1 -> undef4, arg2 -> (arg2 + undef7)}> <l3, l1, true, par{arg1 -> undef8, arg2 -> undef9, arg3 -> undef10}> Fresh variables: undef1, undef4, undef7, undef8, undef9, undef10, Undef variables: undef1, undef4, undef7, undef8, undef9, undef10, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l2, (arg1 = undef1) /\ (arg2 = 0) /\ (arg3 = undef9) /\ (undef1 <= undef8) /\ (undef9 > ~(1)) /\ (undef8 > 0) /\ (undef1 > 0)> <l2, l2, (undef7 > ~(1)) /\ (arg3 > arg2) /\ (arg2 > ~(1)) /\ (undef4 <= arg1) /\ (arg1 > 0) /\ (undef4 > 0), par{arg1 -> undef4, arg2 -> (arg2 + undef7)}> Fresh variables: undef1, undef4, undef7, undef8, undef9, undef10, Undef variables: undef1, undef4, undef7, undef8, undef9, undef10, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l2, l2, 1 <= arg1 /\ 1 + arg2 <= arg3 /\ 1 <= undef4 /\ undef4 <= arg1 /\ 0 <= arg2 /\ 0 <= undef7, {arg1 -> undef4, arg2 -> arg2 + undef7, rest remain the same}> Variables: arg1, arg2, arg3 Precedence: Graph 0 Graph 1 <l0, l2, 1 <= undef1 /\ 1 <= undef8 /\ undef1 <= undef8 /\ 0 <= undef9 /\ arg1 = undef1 /\ arg2 = 0 /\ arg3 = undef9, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.003516 Checking conditional termination of SCC {l2}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.000947s LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.003603s [60047 : 60048] [60047 : 60049] Successful child: 60048
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