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Integ Trans Syste 27634 pair #381737949
details
property
value
status
complete
benchmark
n-9.t2.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n054.star.cs.uiowa.edu
space
From_T2
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp17
runtime (wallclock)
4.78702282906 seconds
cpu usage
7.455058849
max memory
9.36157184E8
stage attributes
key
value
output-size
9073
starexec-result
NO
output
/export/starexec/sandbox2/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox2/benchmark/theBenchmark.smt2 /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- NO Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l8, true> <l1, l2, true, par{p_14^0 -> (0 + x_13^0)}> <l2, l3, ((0 + y_16^0) <= (0 + lt_15^0)) /\ (undef12 = undef12), par{lt_15^0 -> undef12, rt_11^0 -> (0 + st_17^0)}> <l2, l4, ((1 + lt_15^0) <= (0 + y_16^0)) /\ (undef22 = undef22) /\ (undef31 = undef31) /\ (undef27 = (0 + undef31)) /\ (undef24 = undef24) /\ (0 <= (0 + undef27)) /\ ((0 + undef27) <= 0), par{lt_15^0 -> undef22, nd_12^0 -> undef24, rv_18^0 -> undef27}> <l4, l2, true> <l2, l5, ((1 + lt_15^0) <= (0 + y_16^0)) /\ (undef43 = undef43) /\ (undef52 = undef52) /\ (undef45 = undef45), par{lt_15^0 -> undef43, nd_12^0 -> undef45, rv_18^0 -> (0 + undef52)}> <l5, l6, (undef53 = __disjvr_0^0) /\ (__disjvr_0^0 = undef53), par{__disjvr_0^0 -> undef53}> <l6, l7, (undef65 = undef65), par{lt_19^0 -> undef65}> <l7, l2, true> <l8, l1, true> Fresh variables: undef12, undef22, undef24, undef27, undef31, undef43, undef45, undef52, undef53, undef65, Undef variables: undef12, undef22, undef24, undef27, undef31, undef43, undef45, undef52, undef53, undef65, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l2, true> <l2, l3, ((0 + y_16^0) <= (0 + lt_15^0)) /\ (undef12 = undef12), par{lt_15^0 -> undef12}> <l2, l2, ((1 + lt_15^0) <= (0 + y_16^0)) /\ (undef22 = undef22) /\ (undef31 = undef31) /\ (undef27 = (0 + undef31)) /\ (undef24 = undef24) /\ (0 <= (0 + undef27)) /\ ((0 + undef27) <= 0), par{lt_15^0 -> undef22}> <l2, l2, ((1 + lt_15^0) <= (0 + y_16^0)) /\ (undef43 = undef43) /\ (undef52 = undef52) /\ (undef45 = undef45) /\ (undef53 = __disjvr_0^0) /\ (__disjvr_0^0 = undef53) /\ (undef65 = undef65), par{__disjvr_0^0 -> undef53, lt_15^0 -> undef43}> Fresh variables: undef12, undef22, undef24, undef27, undef31, undef43, undef45, undef52, undef53, undef65, Undef variables: undef12, undef22, undef24, undef27, undef31, undef43, undef45, undef52, undef53, undef65, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l2, l2, 1 + lt_15^0 <= y_16^0 /\ undef27 = 0 /\ undef27 = undef31, {lt_15^0 -> undef22, rest remain the same}> <l2, l2, 1 + lt_15^0 <= y_16^0 /\ __disjvr_0^0 = undef53, {__disjvr_0^0 -> undef53, lt_15^0 -> undef43, rest remain the same}> Variables: lt_15^0, y_16^0, __disjvr_0^0 Graph 2: Transitions: Variables: Precedence: Graph 0 Graph 1 <l0, l2, true, {all remain the same}> Graph 2 <l2, l3, y_16^0 <= lt_15^0, {lt_15^0 -> undef12, rest remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 1 ) ( 3 , 2 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** *******************************************************************************************
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