details

property	value
status	complete
benchmark	bf14.t2_fixed.smt2
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n081.star.cs.uiowa.edu
space	From_T2

run statistics

property	value
solver	VeryMax-termCOMP17
configuration	termcomp17
runtime (wallclock)	0.066890001297 seconds
cpu usage	0.064039963
max memory	6324224.0

stage attributes

key	value
output-size	6938
starexec-result	YES

output

/export/starexec/sandbox/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox/benchmark/theBenchmark.smt2 /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l18, true> <l1, l2, ((0 + nodecount^0) <= (0 + i^0))> <l1, l3, ((1 + i^0) <= (0 + nodecount^0)), par{i^0 -> (1 + i^0)}> <l4, l5, true, par{i^0 -> (1 + i^0)}> <l4, l2, true> <l6, l3, ((0 + edgecount^0) <= (0 + i^0)), par{i^0 -> 0}> <l6, l4, ((1 + i^0) <= (0 + edgecount^0)) /\ (undef41 = undef41) /\ (undef42 = undef42), par{x^0 -> undef41, y^0 -> undef42}> <l7, l8, true, par{j^0 -> (1 + j^0)}> <l9, l10, ((0 + edgecount^0) <= (0 + j^0)), par{i^0 -> (1 + i^0)}> <l9, l7, ((1 + j^0) <= (0 + edgecount^0)) /\ (undef62 = undef62) /\ (undef63 = undef63), par{x^0 -> undef62, y^0 -> undef63}> <l11, l5, ((0 + nodecount^0) <= (0 + i^0)), par{i^0 -> 0}> <l11, l8, ((1 + i^0) <= (0 + nodecount^0)), par{j^0 -> 0}> <l12, l13, true> <l14, l15, true> <l15, l12, true, par{i^0 -> (1 + i^0)}> <l16, l14, ((1 + source^0) <= (0 + i^0))> <l16, l14, ((1 + i^0) <= (0 + source^0))> <l16, l15, ((0 + i^0) <= (0 + source^0)) /\ ((0 + source^0) <= (0 + i^0))> <l13, l10, ((0 + nodecount^0) <= (0 + i^0)), par{i^0 -> 0}> <l13, l16, ((1 + i^0) <= (0 + nodecount^0))> <l10, l11, true> <l8, l9, true> <l5, l6, true> <l3, l1, true> <l17, l12, true, par{edgecount^0 -> 14, i^0 -> 0, nodecount^0 -> 5, source^0 -> 0}> <l18, l17, true> Fresh variables: undef41, undef42, undef62, undef63, Undef variables: undef41, undef42, undef62, undef63, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l12, (14 = 14) /\ (i^0 = 0) /\ (5 = 5) /\ (0 = 0)> <l3, l2, ((0 + 5) <= (0 + i^0))> <l3, l3, ((1 + i^0) <= (0 + 5)), par{i^0 -> (1 + i^0)}> <l5, l3, ((0 + 14) <= (0 + i^0)), par{i^0 -> 0}> <l5, l5, ((1 + i^0) <= (0 + 14)) /\ (undef41 = undef41) /\ (undef42 = undef42), par{i^0 -> (1 + i^0)}> <l5, l2, ((1 + i^0) <= (0 + 14)) /\ (undef41 = undef41) /\ (undef42 = undef42)> <l8, l5, ((0 + 14) <= (0 + j^0)) /\ ((0 + 5) <= (0 + (1 + i^0))), par{i^0 -> 0}> <l8, l8, ((0 + 14) <= (0 + j^0)) /\ ((1 + (1 + i^0)) <= (0 + 5)), par{i^0 -> (1 + i^0), j^0 -> 0}> <l8, l8, ((1 + j^0) <= (0 + 14)) /\ (undef62 = undef62) /\ (undef63 = undef63), par{j^0 -> (1 + j^0)}> <l12, l8, ((0 + 5) <= (0 + i^0)) /\ ((1 + 0) <= (0 + 5)), par{i^0 -> 0, j^0 -> 0}> <l12, l12, ((1 + i^0) <= (0 + 5)) /\ ((1 + 0) <= (0 + i^0)), par{i^0 -> (1 + i^0)}> <l12, l12, ((1 + i^0) <= (0 + 5)) /\ ((1 + i^0) <= (0 + 0)), par{i^0 -> (1 + i^0)}> <l12, l12, ((1 + i^0) <= (0 + 5)) /\ ((0 + i^0) <= (0 + 0)) /\ ((0 + 0) <= (0 + i^0)), par{i^0 -> (1 + i^0)}> Fresh variables: undef41, undef42, undef62, undef63, Undef variables: undef41, undef42, undef62, undef63, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l12, l12, 1 <= i^0 /\ i^0 <= 4, {i^0 -> 1 + i^0, rest remain the same}> <l12, l12, 1 + i^0 <= 0, {i^0 -> 1 + i^0, rest remain the same}> popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to Integ Trans Syste 27634