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Integ Trans Syste 27634 pair #381738268
details
property
value
status
complete
benchmark
Velroyen08-ex05.jar-obl-8.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n054.star.cs.uiowa.edu
space
From_AProVE_2014
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp17
runtime (wallclock)
4.19786596298 seconds
cpu usage
5.291126068
max memory
2.94858752E8
stage attributes
key
value
output-size
3368
starexec-result
NO
output
/export/starexec/sandbox2/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox2/benchmark/theBenchmark.smt2 /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- NO Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l3, true> <l1, l1, (undef1 <= arg1) /\ (arg1 > 0) /\ (undef1 > 0), par{arg1 -> undef1}> <l2, l1, (undef3 <= arg1) /\ (arg2 > ~(1)) /\ (arg1 > 0) /\ (undef3 > 0), par{arg1 -> undef3}> <l3, l2, true, par{arg1 -> undef5, arg2 -> undef6}> Fresh variables: undef1, undef3, undef5, undef6, Undef variables: undef1, undef3, undef5, undef6, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l1, (arg1 = undef3) /\ (undef3 <= undef5) /\ (undef6 > ~(1)) /\ (undef5 > 0) /\ (undef3 > 0)> <l1, l1, (undef1 <= arg1) /\ (arg1 > 0) /\ (undef1 > 0), par{arg1 -> undef1}> Fresh variables: undef1, undef3, undef5, undef6, Undef variables: undef1, undef3, undef5, undef6, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l1, l1, undef1 <= arg1 /\ 1 <= arg1 /\ 1 <= undef1, {arg1 -> undef1, rest remain the same}> Variables: arg1 Precedence: Graph 0 Graph 1 <l0, l1, undef3 <= undef5 /\ 0 <= undef6 /\ 1 <= undef3 /\ 1 <= undef5 /\ arg1 = undef3, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 1 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.001889 Checking conditional termination of SCC {l1}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.000600s LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.001995s [51605 : 51606] [51605 : 51607] Solving with 1 template(s).
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