Integ Trans Syste 27634 pair #381738374

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details
property value
status timeout (wallclock)
benchmark Test4.jar-obl-10.smt2
ran by Akihisa Yamada
cpu timeout 1200 seconds
wallclock timeout 300 seconds
memory limit 137438953472 bytes
space From_AProVE_2014
run statistics
property value
solver Ctrl
configuration Transition
runtime (wallclock) 301.007306099 seconds
cpu usage 421.532219257
max memory 4.6759936E7
stage attributes

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