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Integ Trans Syste 27634 pair #381738394
details
property
value
status
complete
benchmark
StupidArray.jar-obl-8.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n026.star.cs.uiowa.edu
space
From_AProVE_2014
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp17
runtime (wallclock)
0.0301110744476 seconds
cpu usage
0.026844304
max memory
4259840.0
stage attributes
key
value
output-size
3086
starexec-result
YES
output
/export/starexec/sandbox2/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox2/benchmark/theBenchmark.smt2 /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l3, true> <l1, l2, (undef1 <= arg1) /\ (arg2 > ~(1)) /\ (arg1 > 0) /\ (undef1 > 0), par{arg1 -> undef1, arg2 -> (arg2 + 1), arg3 -> arg2}> <l2, l2, (arg3 > arg2) /\ (arg3 > ~(1)) /\ (undef4 <= arg1) /\ (arg1 > 0) /\ (undef4 > 0), par{arg1 -> undef4, arg2 -> (arg3 + 1)}> <l3, l1, true, par{arg1 -> undef7, arg2 -> undef8, arg3 -> undef9}> Fresh variables: undef1, undef4, undef7, undef8, undef9, Undef variables: undef1, undef4, undef7, undef8, undef9, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l2, (arg1 = undef1) /\ (arg2 = (undef8 + 1)) /\ (arg3 = undef8) /\ (undef1 <= undef7) /\ (undef8 > ~(1)) /\ (undef7 > 0) /\ (undef1 > 0)> <l2, l2, (arg3 > arg2) /\ (arg3 > ~(1)) /\ (undef4 <= arg1) /\ (arg1 > 0) /\ (undef4 > 0), par{arg1 -> undef4, arg2 -> (arg3 + 1)}> Fresh variables: undef1, undef4, undef7, undef8, undef9, Undef variables: undef1, undef4, undef7, undef8, undef9, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l2, l2, 1 <= arg1 /\ 1 + arg2 <= arg3 /\ 1 <= undef4 /\ undef4 <= arg1 /\ 0 <= arg3, {arg1 -> undef4, arg2 -> 1 + arg3, rest remain the same}> Variables: arg1, arg2, arg3 Precedence: Graph 0 Graph 1 <l0, l2, 1 <= undef1 /\ 1 <= undef7 /\ undef1 <= undef7 /\ 0 <= undef8 /\ arg2 = 1 + undef8 /\ arg1 = undef1 /\ arg3 = undef8, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.003443 �[33mSome transition disabled by a set of invariant(s):�[0m �[36mInvariant at l2: arg3 <= arg2�[0m �[33mStrengthening and disabling transitions...�[0m > It's unfeasible. Removing transition: <l2, l2, 1 <= arg1 /\ 1 + arg2 <= arg3 /\ 1 <= undef4 /\ undef4 <= arg1 /\ 0 <= arg3, {arg1 -> undef4, arg2 -> 1 + arg3, rest remain the same}> Checking unfeasibility... Time used: 2.8e-05 Analyzing SCC {l2}... No cycles found. �[32mProgram Terminates�[0m
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