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Integ Trans Syste 27634 pair #381738477
details
property
value
status
complete
benchmark
rewrite.t2.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n037.star.cs.uiowa.edu
space
From_T2
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp17
runtime (wallclock)
0.0401921272278 seconds
cpu usage
0.044860187
max memory
3.190784E7
stage attributes
key
value
output-size
2771
starexec-result
NO
output
/export/starexec/sandbox/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox/benchmark/theBenchmark.smt2 /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- NO Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l4, true> <l1, l2, (undef4 = undef4) /\ (undef3 = (0 + undef4)) /\ (undef2 = undef2) /\ ((1 + undef3) <= (0 + undef2)) /\ ((0 + undef2) <= (1 + undef3)), par{x^0 -> (0 + undef2), x_next^0 -> undef2}> <l2, l1, true> <l3, l1, true> <l4, l3, true> Fresh variables: undef2, undef3, undef4, Undef variables: undef2, undef3, undef4, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l1, true> <l1, l1, (undef4 = undef4) /\ (undef3 = (0 + undef4)) /\ (undef2 = undef2) /\ ((1 + undef3) <= (0 + undef2)) /\ ((0 + undef2) <= (1 + undef3))> Fresh variables: undef2, undef3, undef4, Undef variables: undef2, undef3, undef4, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l1, l1, undef3 = undef4 /\ undef2 = 1 + undef3, {all remain the same}> Variables: Precedence: Graph 0 Graph 1 <l0, l1, true, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 1 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.001164 > No variable changes in termination graph. Checking conditional unfeasibility... Termination failed. Trying to show unreachability... Proving unreachability of entry: <l0, l1, true, {all remain the same}> LOG: CALL check - Post:1 <= 0 - Process 1 * Exit transition: <l0, l1, true, {all remain the same}> * Postcondition : 1 <= 0 LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.000182s
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