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Integ Trans Syste 27634 pair #381738484
details
property
value
status
complete
benchmark
Et1.jar-obl-8.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n053.star.cs.uiowa.edu
space
From_AProVE_2014
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp17
runtime (wallclock)
6.20789599419 seconds
cpu usage
13.375199056
max memory
2.55270912E8
stage attributes
key
value
output-size
5081
starexec-result
YES
output
/export/starexec/sandbox2/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox2/benchmark/theBenchmark.smt2 /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l3, true> <l1, l2, (undef3 > ~(1)) /\ (arg2 > 1) /\ (undef4 > ~(1)) /\ (arg1 > 0), par{arg1 -> (0 - undef4), arg2 -> (0 - undef3)}> <l2, l2, (arg2 < arg1), par{arg1 -> (arg1 + 1), arg2 -> (arg2 + arg1)}> <l3, l1, true, par{arg1 -> undef7, arg2 -> undef8}> Fresh variables: undef3, undef4, undef7, undef8, Undef variables: undef3, undef4, undef7, undef8, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l2, (arg1 = (0 - undef4)) /\ (arg2 = (0 - undef3)) /\ (undef3 > ~(1)) /\ (undef8 > 1) /\ (undef4 > ~(1)) /\ (undef7 > 0)> <l2, l2, (arg2 < arg1), par{arg1 -> (arg1 + 1), arg2 -> (arg2 + arg1)}> Fresh variables: undef3, undef4, undef7, undef8, Undef variables: undef3, undef4, undef7, undef8, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l2, l2, 1 + arg2 <= arg1, {arg1 -> 1 + arg1, arg2 -> arg1 + arg2, rest remain the same}> Variables: arg1, arg2 Precedence: Graph 0 Graph 1 <l0, l2, 1 <= undef7 /\ 0 <= undef3 /\ 0 <= undef4 /\ 2 <= undef8 /\ arg1 + undef4 = 0 /\ arg2 + undef3 = 0, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.00223 Checking conditional termination of SCC {l2}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.000594s LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.001694s [49020 : 49026] [49020 : 49027] Successful child: 49026
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