details

property	value
status	complete
benchmark	Velroyen08-ex01.jar-obl-8.smt2
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n021.star.cs.uiowa.edu
space	From_AProVE_2014

run statistics

property	value
solver	VeryMax-termCOMP17
configuration	termcomp17
runtime (wallclock)	8.41329407692 seconds
cpu usage	18.727917782
max memory	2.54971904E8

stage attributes

key	value
output-size	5707
starexec-result	NO

output

/export/starexec/sandbox/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox/benchmark/theBenchmark.smt2 /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- NO Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l4, true> <l1, l2, (undef3 > ~(1)) /\ (arg2 > 1) /\ ((undef4 - (2 * undef5)) = 0) /\ (undef4 > ~(1)) /\ (arg1 > 0)> <l2, l3, (undef8 > ~(1)) /\ (arg2 > 1) /\ ((undef9 - (2 * undef10)) = 0) /\ (undef9 > ~(1)) /\ (arg1 > 0) /\ ((undef9 - (2 * undef10)) < 2) /\ ((undef9 - (2 * undef10)) >= 0), par{arg1 -> (0 - undef8), arg2 -> undef7}> <l3, l3, (arg1 < 0), par{arg1 -> (arg1 - 1), arg2 -> undef12}> <l4, l1, true, par{arg1 -> undef13, arg2 -> undef14}> Fresh variables: undef3, undef4, undef5, undef7, undef8, undef9, undef10, undef12, undef13, undef14, Undef variables: undef3, undef4, undef5, undef7, undef8, undef9, undef10, undef12, undef13, undef14, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l3, (arg1 = (0 - undef8)) /\ (undef3 > ~(1)) /\ (undef14 > 1) /\ ((undef4 - (2 * undef5)) = 0) /\ (undef4 > ~(1)) /\ (undef13 > 0) /\ (undef8 > ~(1)) /\ (undef14 > 1) /\ ((undef9 - (2 * undef10)) = 0) /\ (undef9 > ~(1)) /\ (undef13 > 0) /\ ((undef9 - (2 * undef10)) < 2) /\ ((undef9 - (2 * undef10)) >= 0)> <l3, l3, (arg1 < 0), par{arg1 -> (arg1 - 1)}> Fresh variables: undef3, undef4, undef5, undef7, undef8, undef9, undef10, undef12, undef13, undef14, Undef variables: undef3, undef4, undef5, undef7, undef8, undef9, undef10, undef12, undef13, undef14, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l3, l3, 1 + arg1 <= 0, {arg1 -> -1 + arg1, rest remain the same}> Variables: arg1 Precedence: Graph 0 Graph 1 <l0, l3, 1 <= undef13 /\ 2 <= undef14 /\ 0 <= undef3 /\ 0 <= undef4 /\ 0 <= undef8 /\ 0 <= undef9 /\ arg1 + undef8 = 0 /\ undef4 = 2*undef5 /\ undef9 = 2*undef10, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 3 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.001927 Checking conditional termination of SCC {l3}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.000427s LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.001100s [25974 : 25975] [25974 : 25976] popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to Integ Trans Syste 27634