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Integ Trans Syste 27634 pair #381738538
details
property
value
status
complete
benchmark
Et1-rec.jar-obl-8.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n023.star.cs.uiowa.edu
space
From_AProVE_2014
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp17
runtime (wallclock)
6.22686314583 seconds
cpu usage
13.412473298
max memory
2.42991104E8
stage attributes
key
value
output-size
6996
starexec-result
YES
output
/export/starexec/sandbox/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox/benchmark/theBenchmark.smt2 /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l3, true> <l1, l2, (arg1 > 0) /\ (0 = arg2), par{arg1 -> 0, arg2 -> 0, arg3 -> 0}> <l1, l2, (arg1 > 0) /\ (undef7 > ~(1)) /\ (1 = arg2), par{arg1 -> 0, arg2 -> (0 - undef7), arg3 -> 0}> <l1, l2, (undef11 > ~(1)) /\ (arg2 > 1) /\ (undef12 > ~(1)) /\ (arg1 > 0), par{arg1 -> (0 - undef12), arg2 -> (0 - undef11), arg3 -> (0 - undef12)}> <l2, l2, (arg1 < arg2) /\ ((arg2 + 1) > arg2) /\ (arg1 < (arg2 + 1)) /\ (arg1 = arg3), par{arg1 -> (arg1 + arg2), arg2 -> (arg2 + 1), arg3 -> (arg1 + arg2)}> <l3, l1, true, par{arg1 -> undef16, arg2 -> undef17, arg3 -> undef18}> Fresh variables: undef7, undef11, undef12, undef16, undef17, undef18, Undef variables: undef7, undef11, undef12, undef16, undef17, undef18, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l2, (undef16 > 0) /\ (0 = undef17), par{arg1 -> 0, arg2 -> 0, arg3 -> 0}> <l0, l2, (undef16 > 0) /\ (undef7 > ~(1)) /\ (1 = undef17), par{arg1 -> 0, arg2 -> (0 - undef7), arg3 -> 0}> <l0, l2, (undef11 > ~(1)) /\ (undef17 > 1) /\ (undef12 > ~(1)) /\ (undef16 > 0), par{arg1 -> (0 - undef12), arg2 -> (0 - undef11), arg3 -> (0 - undef12)}> <l2, l2, (arg1 < arg2) /\ ((arg2 + 1) > arg2) /\ (arg1 < (arg2 + 1)) /\ (arg1 = arg3), par{arg1 -> (arg1 + arg2), arg2 -> (arg2 + 1), arg3 -> (arg1 + arg2)}> Fresh variables: undef7, undef11, undef12, undef16, undef17, undef18, Undef variables: undef7, undef11, undef12, undef16, undef17, undef18, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l2, l2, 1 + arg1 <= arg2 /\ arg1 = arg3, {arg1 -> arg1 + arg2, arg2 -> 1 + arg2, arg3 -> arg1 + arg2, rest remain the same}> Variables: arg1, arg2, arg3 Precedence: Graph 0 Graph 1 <l0, l2, 1 <= undef16 /\ undef17 = 0, {arg1 -> 0, arg2 -> 0, arg3 -> 0, rest remain the same}> <l0, l2, 0 <= undef7 /\ 1 <= undef16 /\ undef17 = 1, {arg1 -> 0, arg2 -> -undef7, arg3 -> 0, rest remain the same}> <l0, l2, 0 <= undef11 /\ 0 <= undef12 /\ 1 <= undef16 /\ 2 <= undef17, {arg1 -> -undef12, arg2 -> -undef11, arg3 -> -undef12, rest remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.003172 Checking conditional termination of SCC {l2}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.000720s
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