Integ Trans Syste 27634 pair #381738571

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details
property value
status timeout (wallclock)
benchmark polling.bug.t2.smt2
ran by Akihisa Yamada
cpu timeout 1200 seconds
wallclock timeout 300 seconds
memory limit 137438953472 bytes
space From_T2
run statistics
property value
solver Ctrl
configuration Transition
runtime (wallclock) 301.006587982 seconds
cpu usage 400.785708467
max memory 4.380672E7
stage attributes

unavailable

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