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Integ Trans Syste 27634 pair #381738586
details
property
value
status
complete
benchmark
Fibonacci.jar-obl-8.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n073.star.cs.uiowa.edu
space
From_AProVE_2014
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp17
runtime (wallclock)
0.0322239398956 seconds
cpu usage
0.028805808
max memory
4648960.0
stage attributes
key
value
output-size
2955
starexec-result
YES
output
/export/starexec/sandbox/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox/benchmark/theBenchmark.smt2 /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l5, true> <l1, l2, (arg1 > 0) /\ (arg2 > ~(1)), par{arg1 -> arg2, arg2 -> undef2}> <l2, l2, (arg1 > 1) /\ ((arg1 - 1) < arg1), par{arg1 -> (arg1 - 1), arg2 -> undef4}> <l2, l3, (2 = arg1), par{arg1 -> 2, arg2 -> 0}> <l2, l3, (arg1 > 1) /\ ((arg1 - 1) < arg1), par{arg2 -> (arg1 - 2)}> <l4, l3, (arg1 > 0), par{arg2 -> (arg1 - 2)}> <l3, l2, (arg1 > 1) /\ (arg2 < arg1), par{arg1 -> arg2, arg2 -> undef12}> <l5, l1, true, par{arg1 -> undef13, arg2 -> undef14}> Fresh variables: undef2, undef4, undef12, undef13, undef14, Undef variables: undef2, undef4, undef12, undef13, undef14, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l2, (arg1 = undef14) /\ (undef13 > 0) /\ (undef14 > ~(1))> <l2, l2, (arg1 > 1) /\ ((arg1 - 1) < arg1), par{arg1 -> (arg1 - 1)}> <l2, l2, (2 = arg1) /\ (2 > 1) /\ (0 < 2), par{arg1 -> 0}> <l2, l2, (arg1 > 1) /\ ((arg1 - 1) < arg1) /\ (arg1 > 1) /\ ((arg1 - 2) < arg1), par{arg1 -> (arg1 - 2)}> Fresh variables: undef2, undef4, undef12, undef13, undef14, Undef variables: undef2, undef4, undef12, undef13, undef14, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l2, l2, 2 <= arg1, {arg1 -> -1 + arg1, rest remain the same}> <l2, l2, arg1 = 2, {arg1 -> 0, rest remain the same}> <l2, l2, 2 <= arg1, {arg1 -> -2 + arg1, rest remain the same}> Variables: arg1 Precedence: Graph 0 Graph 1 <l0, l2, 0 <= undef14 /\ 1 <= undef13 /\ arg1 = undef14, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.004862 Checking conditional termination of SCC {l2}... LOG: CALL solveLinear
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