Integ Trans Syste 27634 pair #381738607

loading
details
property value
status complete
benchmark fibcall.t2.smt2
ran by Akihisa Yamada
cpu timeout 1200 seconds
wallclock timeout 300 seconds
memory limit 137438953472 bytes
execution host n054.star.cs.uiowa.edu
space From_T2
run statistics
property value
solver Ctrl
configuration Transition
runtime (wallclock) 13.418982029 seconds
cpu usage 13.903105945
max memory 3.0113792E7
stage attributes
key value
output-size 4153
starexec-result YES
loading output popout

output may be truncated. 'popout' for the full output.

loading job log

	
				popout
			
actions all output return to Integ Trans Syste 27634