details

property	value
status	complete
benchmark	consts2nt.t2.smt2
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n091.star.cs.uiowa.edu
space	From_T2

run statistics

property	value
solver	VeryMax-termCOMP17
configuration	termcomp17
runtime (wallclock)	4.46278381348 seconds
cpu usage	6.261549448
max memory	2.66555392E8

stage attributes

key	value
output-size	7593
starexec-result	NO

output

/export/starexec/sandbox/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox/benchmark/theBenchmark.smt2 /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- NO Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l4, true> <l1, l2, (undef2 = ((0 + __const_1000^0) + x^0)) /\ (1 <= (0 + undef2)), par{x^0 -> undef2}> <l2, l1, true> <l3, l1, true> <l4, l3, true> Fresh variables: undef2, Undef variables: undef2, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l1, true> <l1, l1, (undef2 = ((0 + __const_1000^0) + x^0)) /\ (1 <= (0 + undef2)), par{x^0 -> undef2}> Fresh variables: undef2, Undef variables: undef2, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l1, l1, 1 <= undef2 /\ __const_1000^0 + x^0 = undef2, {x^0 -> undef2, rest remain the same}> Variables: __const_1000^0, x^0 Precedence: Graph 0 Graph 1 <l0, l1, true, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 1 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.001786 Checking conditional termination of SCC {l1}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.000653s LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.002082s [52250 : 52251] [52250 : 52252] popout

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job log

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actions

all output return to Integ Trans Syste 27634