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Integ Trans Syste 27634 pair #381738862
details
property
value
status
complete
benchmark
Velroyen08-whileBreak.jar-obl-8.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n087.star.cs.uiowa.edu
space
From_AProVE_2014
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp17
runtime (wallclock)
9.34913802147 seconds
cpu usage
21.399772786
max memory
4.7816704E8
stage attributes
key
value
output-size
24693
starexec-result
NO
output
/export/starexec/sandbox/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox/benchmark/theBenchmark.smt2 /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- NO Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l4, true> <l1, l2, (arg1 > 0) /\ (arg2 > ~(1)), par{arg1 -> arg2, arg2 -> undef2}> <l2, l3, (arg1 < 21) /\ (arg1 > 10), par{arg1 -> (arg1 - 1), arg2 -> undef4}> <l2, l3, (arg1 > 20), par{arg1 -> (arg1 + 1), arg2 -> undef6}> <l3, l2, (arg1 < 30), par{arg2 -> undef8}> <l3, l2, (arg1 > 30), par{arg2 -> undef10}> <l4, l1, true, par{arg1 -> undef11, arg2 -> undef12}> Fresh variables: undef2, undef4, undef6, undef8, undef10, undef11, undef12, Undef variables: undef2, undef4, undef6, undef8, undef10, undef11, undef12, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l2, (arg1 = undef12) /\ (undef11 > 0) /\ (undef12 > ~(1))> <l2, l2, (arg1 < 21) /\ (arg1 > 10) /\ ((arg1 - 1) < 30), par{arg1 -> (arg1 - 1)}> <l2, l2, (arg1 > 20) /\ ((arg1 + 1) < 30), par{arg1 -> (arg1 + 1)}> <l2, l2, (arg1 > 20) /\ ((arg1 + 1) > 30), par{arg1 -> (arg1 + 1)}> Fresh variables: undef2, undef4, undef6, undef8, undef10, undef11, undef12, Undef variables: undef2, undef4, undef6, undef8, undef10, undef11, undef12, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l2, l2, arg1 <= 20 /\ 11 <= arg1, {arg1 -> -1 + arg1, rest remain the same}> <l2, l2, 21 <= arg1 /\ arg1 <= 28, {arg1 -> 1 + arg1, rest remain the same}> <l2, l2, 30 <= arg1, {arg1 -> 1 + arg1, rest remain the same}> Variables: arg1 Precedence: Graph 0 Graph 1 <l0, l2, 0 <= undef12 /\ 1 <= undef11 /\ arg1 = undef12, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.003854 Checking conditional termination of SCC {l2}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.001023s
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