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Integ Trans Syste 27634 pair #381738903
details
property
value
status
complete
benchmark
p-50.t2.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n085.star.cs.uiowa.edu
space
From_T2
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp17
runtime (wallclock)
0.0224637985229 seconds
cpu usage
0.018609579
max memory
3702784.0
stage attributes
key
value
output-size
2571
starexec-result
YES
output
/export/starexec/sandbox/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox/benchmark/theBenchmark.smt2 /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l3, true> <l1, l2, (undef6 = undef6) /\ (undef7 = undef7) /\ (undef4 = undef4) /\ (undef5 = undef5) /\ (undef10 = undef10) /\ (undef9 = undef9) /\ (undef11 = undef11) /\ (undef3 = undef3) /\ (undef1 = undef1), par{Result_4^0 -> undef1, devExt_7^0 -> undef3, i_12^0 -> undef4, irp_11^0 -> undef5, loop_count_14^0 -> undef6, loop_max_13^0 -> undef7, lt_46^0 -> (0 + cnt_58^0), nPacketsOld_9^0 -> undef9, nPackets_10^0 -> undef10, request_8^0 -> undef11}> <l3, l1, true> Fresh variables: undef1, undef3, undef4, undef5, undef6, undef7, undef9, undef10, undef11, Undef variables: undef1, undef3, undef4, undef5, undef6, undef7, undef9, undef10, undef11, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l2, (undef6 = undef6) /\ (undef7 = undef7) /\ (undef4 = undef4) /\ (undef5 = undef5) /\ (undef10 = undef10) /\ (undef9 = undef9) /\ (undef11 = undef11) /\ (undef3 = undef3) /\ (undef1 = undef1)> Fresh variables: undef1, undef3, undef4, undef5, undef6, undef7, undef9, undef10, undef11, Undef variables: undef1, undef3, undef4, undef5, undef6, undef7, undef9, undef10, undef11, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: Variables: Precedence: Graph 0 Graph 1 <l0, l2, true, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Analyzing SCC {l2}... No cycles found. �[32mProgram Terminates�[0m
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