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Integ Trans Syste 27634 pair #381738922
details
property
value
status
complete
benchmark
mirrorIntervSim_rec.jar-obl-8.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n058.star.cs.uiowa.edu
space
From_AProVE_2014
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp17
runtime (wallclock)
11.9035248756 seconds
cpu usage
31.185697088
max memory
1.081176064E9
stage attributes
key
value
output-size
7056
starexec-result
NO
output
/export/starexec/sandbox2/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox2/benchmark/theBenchmark.smt2 /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- NO Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l3, true> <l1, l2, ((arg2 + 28) > arg2) /\ (arg2 > ~(1)) /\ (arg1 > 0), par{arg1 -> (arg2 + 28), arg2 -> undef2}> <l2, l2, (arg1 > 35), par{arg1 -> 0, arg2 -> undef4}> <l2, l2, (arg1 < 31) /\ (arg1 < 36) /\ (arg1 > 0), par{arg1 -> (arg1 - 1), arg2 -> undef6}> <l2, l2, (arg1 > 30) /\ (arg1 < 36), par{arg1 -> 35, arg2 -> undef8}> <l3, l1, true, par{arg1 -> undef9, arg2 -> undef10}> Fresh variables: undef2, undef4, undef6, undef8, undef9, undef10, Undef variables: undef2, undef4, undef6, undef8, undef9, undef10, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l2, (arg1 = (undef10 + 28)) /\ ((undef10 + 28) > undef10) /\ (undef10 > ~(1)) /\ (undef9 > 0)> <l2, l2, (arg1 > 35), par{arg1 -> 0}> <l2, l2, (arg1 < 31) /\ (arg1 < 36) /\ (arg1 > 0), par{arg1 -> (arg1 - 1)}> <l2, l2, (arg1 > 30) /\ (arg1 < 36), par{arg1 -> 35}> Fresh variables: undef2, undef4, undef6, undef8, undef9, undef10, Undef variables: undef2, undef4, undef6, undef8, undef9, undef10, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l2, l2, 36 <= arg1, {arg1 -> 0, rest remain the same}> <l2, l2, 1 <= arg1 /\ arg1 <= 30, {arg1 -> -1 + arg1, rest remain the same}> <l2, l2, 31 <= arg1 /\ arg1 <= 35, {arg1 -> 35, rest remain the same}> Variables: arg1 Precedence: Graph 0 Graph 1 <l0, l2, 1 <= undef9 /\ 0 <= undef10 /\ arg1 = 28 + undef10, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.006005 Checking conditional termination of SCC {l2}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.001186s
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