details

property	value
status	complete
benchmark	ex1.t2.smt2
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n038.star.cs.uiowa.edu
space	From_T2

run statistics

property	value
solver	VeryMax-termCOMP17
configuration	termcomp17
runtime (wallclock)	34.0177919865 seconds
cpu usage	64.879704997
max memory	2.14360064E8

stage attributes

key	value
output-size	9555
starexec-result	NO

output

/export/starexec/sandbox/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox/benchmark/theBenchmark.smt2 /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- NO Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l5, true> <l1, l2, (undef3 = undef3), par{i^0 -> (1 + i^0), j^0 -> (2 + j^0), ret_pair5^0 -> undef3}> <l1, l3, true> <l2, l1, true> <l4, l2, true, par{i^0 -> 0, j^0 -> 0}> <l5, l4, true> Fresh variables: undef3, Undef variables: undef3, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l2, (i^0 = 0) /\ (j^0 = 0)> <l2, l2, (undef3 = undef3), par{i^0 -> (1 + i^0), j^0 -> (2 + j^0)}> <l2, l3, true> Fresh variables: undef3, Undef variables: undef3, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l2, l2, true, {i^0 -> 1 + i^0, j^0 -> 2 + j^0, rest remain the same}> Variables: i^0, j^0 Graph 2: Transitions: Variables: Precedence: Graph 0 Graph 1 <l0, l2, i^0 = 0 /\ j^0 = 0, {all remain the same}> Graph 2 <l2, l3, true, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 1 ) ( 3 , 2 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.002067 Checking conditional termination of SCC {l2}... popout

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job log

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actions

all output return to Integ Trans Syste 27634