details

property	value
status	complete
benchmark	ax_test_2.t2.smt2
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n016.star.cs.uiowa.edu
space	From_T2

run statistics

property	value
solver	VeryMax-termCOMP17
configuration	termcomp17
runtime (wallclock)	0.0345339775085 seconds
cpu usage	0.037327668
max memory	3.362816E7

stage attributes

key	value
output-size	2527
starexec-result	NO

output

/export/starexec/sandbox2/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox2/benchmark/theBenchmark.smt2 /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- NO Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l4, true> <l1, l2, true> <l2, l1, true> <l3, l1, (undef4 = 0) /\ (undef5 = 1), par{p^0 -> 0}> <l4, l3, true> Fresh variables: undef4, undef5, Undef variables: undef4, undef5, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l1, (undef4 = 0) /\ (undef5 = 1)> <l1, l1, true> Fresh variables: undef4, undef5, Undef variables: undef4, undef5, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l1, l1, true, {all remain the same}> Variables: Precedence: Graph 0 Graph 1 <l0, l1, undef4 = 0 /\ undef5 = 1, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 1 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.000942 > No variable changes in termination graph. Checking conditional unfeasibility... Termination failed. Trying to show unreachability... Proving unreachability of entry: <l0, l1, undef4 = 0 /\ undef5 = 1, {all remain the same}> LOG: CALL check - Post:1 <= 0 - Process 1 * Exit transition: <l0, l1, undef4 = 0 /\ undef5 = 1, {all remain the same}> * Postcondition : 1 <= 0 LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.000300s popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to Integ Trans Syste 27634