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Integ Trans Syste 27634 pair #381739119
details
property
value
status
complete
benchmark
curious.t2_fixed.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n074.star.cs.uiowa.edu
space
From_T2
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp17
runtime (wallclock)
4.21697402 seconds
cpu usage
5.327412434
max memory
2.98692608E8
stage attributes
key
value
output-size
3655
starexec-result
NO
output
/export/starexec/sandbox/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox/benchmark/theBenchmark.smt2 /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- NO Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l6, true> <l1, l2, (0 <= (0 + b^0)), par{b^0 -> 1}> <l2, l3, ((1 + b^0) <= 0)> <l2, l3, (1 <= (0 + b^0))> <l3, l4, true, par{b^0 -> 0}> <l4, l1, true> <l5, l1, true> <l6, l5, true> Fresh variables: Undef variables: Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l1, true> <l1, l1, (0 <= (0 + b^0)) /\ (1 <= (0 + 1)), par{b^0 -> 0}> Fresh variables: Undef variables: Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l1, l1, 0 <= b^0, {b^0 -> 0, rest remain the same}> Variables: b^0 Precedence: Graph 0 Graph 1 <l0, l1, true, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 1 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.00169 Checking conditional termination of SCC {l1}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.000626s LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.001176s [57417 : 57418] [57417 : 57419] Successful child: 57418
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