details

property	value
status	complete
benchmark	ex05_rec.jar-obl-8.smt2
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n104.star.cs.uiowa.edu
space	From_AProVE_2014

run statistics

property	value
solver	VeryMax-termCOMP17
configuration	termcomp17
runtime (wallclock)	0.0343930721283 seconds
cpu usage	0.036100285
max memory	3.1617024E7

stage attributes

key	value
output-size	2662
starexec-result	NO

output

/export/starexec/sandbox2/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox2/benchmark/theBenchmark.smt2 /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- NO Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l3, true> <l1, l2, (arg1 > 0) /\ (arg2 > ~(1)), par{arg1 -> arg2, arg2 -> undef2}> <l2, l2, true, par{arg2 -> undef4}> <l3, l1, true, par{arg1 -> undef5, arg2 -> undef6}> Fresh variables: undef2, undef4, undef5, undef6, Undef variables: undef2, undef4, undef5, undef6, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l2, (undef5 > 0) /\ (undef6 > ~(1))> <l2, l2, true> Fresh variables: undef2, undef4, undef5, undef6, Undef variables: undef2, undef4, undef5, undef6, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l2, l2, true, {all remain the same}> Variables: Precedence: Graph 0 Graph 1 <l0, l2, 0 <= undef6 /\ 1 <= undef5, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.001254 > No variable changes in termination graph. Checking conditional unfeasibility... Termination failed. Trying to show unreachability... Proving unreachability of entry: <l0, l2, 0 <= undef6 /\ 1 <= undef5, {all remain the same}> LOG: CALL check - Post:1 <= 0 - Process 1 * Exit transition: <l0, l2, 0 <= undef6 /\ 1 <= undef5, {all remain the same}> * Postcondition : 1 <= 0 LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.000277s �[31m> Postcondition is not implied!�[0m popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to Integ Trans Syste 27634