details

property	value
status	complete
benchmark	iecs.t2.smt2
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n058.star.cs.uiowa.edu
space	From_T2

run statistics

property	value
solver	VeryMax-termCOMP17
configuration	termcomp17
runtime (wallclock)	0.0378148555756 seconds
cpu usage	0.05043605
max memory	1.0407936E7

stage attributes

key	value
output-size	2926
starexec-result	YES

output

/export/starexec/sandbox/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox/benchmark/theBenchmark.smt2 /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- YES Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l4, true> <l1, l2, (1 <= (0 + x^0)), par{x^0 -> ((0 + x^0) + (~(1) * y^0)), y^0 -> (1 + y^0)}> <l2, l1, true> <l3, l1, (1 <= (0 + y^0))> <l4, l3, true> Fresh variables: Undef variables: Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l1, (1 <= (0 + y^0))> <l1, l1, (1 <= (0 + x^0)), par{x^0 -> ((0 + x^0) + (~(1) * y^0)), y^0 -> (1 + y^0)}> Fresh variables: Undef variables: Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l1, l1, 1 <= x^0, {x^0 -> x^0 - y^0, y^0 -> 1 + y^0, rest remain the same}> Variables: x^0, y^0 Precedence: Graph 0 Graph 1 <l0, l1, 1 <= y^0, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 1 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.001894 Checking conditional termination of SCC {l1}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.000688s LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.001635s [19441 : 19442] [19441 : 19443] Successful child: 19442 [ Invariant Graph ] �[33mStrengthening and disabling transitions...�[0m popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to Integ Trans Syste 27634