details

property	value
status	complete
benchmark	heidy1.t2.smt2
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n094.star.cs.uiowa.edu
space	From_T2

run statistics

property	value
solver	VeryMax-termCOMP17
configuration	termcomp17
runtime (wallclock)	13.4753940105 seconds
cpu usage	23.766857287
max memory	5.2680704E8

stage attributes

key	value
output-size	4238
starexec-result	NO

output

/export/starexec/sandbox2/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox2/benchmark/theBenchmark.smt2 /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- NO Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l5, true> <l1, l2, true, par{x_1^0 -> 1, y_1^0 -> 1}> <l2, l3, true, par{x_1^0 -> (1 + x_1^0)}> <l3, l2, true> <l2, l4, (2 <= 0)> <l5, l1, true> Fresh variables: Undef variables: Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l2, (x_1^0 = 1)> <l2, l2, true, par{x_1^0 -> (1 + x_1^0)}> Fresh variables: Undef variables: Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l2, l2, true, {x_1^0 -> 1 + x_1^0, rest remain the same}> Variables: x_1^0 Precedence: Graph 0 Graph 1 <l0, l2, x_1^0 = 1, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.001389 Checking conditional termination of SCC {l2}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.000463s LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.000838s [36263 : 36264] [36263 : 36265] Solving with 1 template(s). LOG: CALL solveNonLinearGetFirstSolution popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to Integ Trans Syste 27634