details

property	value
status	complete
benchmark	smagilla-fail.t2.smt2
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n109.star.cs.uiowa.edu
space	From_T2

run statistics

property	value
solver	VeryMax-termCOMP17
configuration	termcomp17
runtime (wallclock)	6.19775891304 seconds
cpu usage	22.375128703
max memory	2.09686528E8

stage attributes

key	value
output-size	5988
starexec-result	NO

output

/export/starexec/sandbox2/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox2/benchmark/theBenchmark.smt2 /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- NO Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l9, true> <l1, l2, true> <l3, l4, true> <l5, l6, true> <l6, l5, true> <l7, l1, ((0 + ___rho_1_^0) <= 0) /\ ((1 + c^0) <= (0 + curr_serv^0)), par{curr_serv^0 -> (~(1) + curr_serv^0)}> <l7, l1, (1 <= (0 + ___rho_1_^0)), par{c^0 -> (~(1) + c^0), curr_serv^0 -> (~(1) + curr_serv^0), resp^0 -> (1 + resp^0)}> <l2, l7, (1 <= (0 + curr_serv^0)) /\ (undef31 = undef31), par{___rho_1_^0 -> undef31}> <l2, l5, ((0 + curr_serv^0) <= 0)> <l8, l1, (undef42 = undef42) /\ (1 <= (0 + undef42)) /\ (undef45 = 4), par{c^0 -> undef42, curr_serv^0 -> (0 + undef45), resp^0 -> 0, servers^0 -> undef45}> <l9, l8, true> Fresh variables: undef31, undef42, undef45, Undef variables: undef31, undef42, undef45, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l1, (c^0 = undef42) /\ (curr_serv^0 = (0 + undef45)) /\ (resp^0 = 0) /\ (undef42 = undef42) /\ (1 <= (0 + undef42)) /\ (undef45 = 4)> <l1, l1, (1 <= (0 + curr_serv^0)) /\ (undef31 = undef31) /\ ((0 + undef31) <= 0) /\ ((1 + c^0) <= (0 + curr_serv^0)), par{curr_serv^0 -> (~(1) + curr_serv^0)}> <l1, l1, (1 <= (0 + curr_serv^0)) /\ (undef31 = undef31) /\ (1 <= (0 + undef31)), par{c^0 -> (~(1) + c^0), curr_serv^0 -> (~(1) + curr_serv^0), resp^0 -> (1 + resp^0)}> <l1, l5, ((0 + curr_serv^0) <= 0)> <l5, l5, true> Fresh variables: undef31, undef42, undef45, Undef variables: undef31, undef42, undef45, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l1, l1, undef31 <= 0 /\ 1 + c^0 <= curr_serv^0 /\ 1 <= curr_serv^0, {curr_serv^0 -> -1 + curr_serv^0, rest remain the same}> <l1, l1, 1 <= curr_serv^0 /\ 1 <= undef31, {c^0 -> -1 + c^0, curr_serv^0 -> -1 + curr_serv^0, resp^0 -> 1 + resp^0, rest remain the same}> Variables: c^0, curr_serv^0, resp^0 Graph 2: Transitions: <l5, l5, true, {all remain the same}> Variables: Precedence: Graph 0 Graph 1 <l0, l1, 1 <= undef42 /\ c^0 = undef42 /\ curr_serv^0 = undef45 /\ resp^0 = 0 /\ undef45 = 4, {all remain the same}> Graph 2 <l1, l5, curr_serv^0 <= 0, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 1 , 1 ) ( 5 , 2 ) ******************************************************************************************* popout

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job log

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actions

all output return to Integ Trans Syste 27634