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Integ Trans Syste 27634 pair #381739844
details
property
value
status
complete
benchmark
simple_swap_call.t2.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n007.star.cs.uiowa.edu
space
From_T2
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp17
runtime (wallclock)
0.0229139328003 seconds
cpu usage
0.019138645
max memory
3825664.0
stage attributes
key
value
output-size
1887
starexec-result
YES
output
/export/starexec/sandbox2/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox2/benchmark/theBenchmark.smt2 /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l5, true> <l1, l2, true> <l1, l2, true> <l2, l3, true> <l4, l1, (undef12 = undef12), par{i^0 -> 0, j^0 -> 1, tmp^0 -> undef12}> <l5, l4, true> Fresh variables: undef12, Undef variables: undef12, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l3, (undef12 = undef12)> <l0, l3, (undef12 = undef12)> Fresh variables: undef12, Undef variables: undef12, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: Variables: Precedence: Graph 0 Graph 1 <l0, l3, true, {all remain the same}> <l0, l3, true, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 3 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Analyzing SCC {l3}... No cycles found. �[32mProgram Terminates�[0m
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