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Integ Trans Syste 27634 pair #381740030
details
property
value
status
complete
benchmark
d.t2.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n105.star.cs.uiowa.edu
space
From_T2
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp17
runtime (wallclock)
6.91510009766 seconds
cpu usage
15.673843119
max memory
9.8633728E8
stage attributes
key
value
output-size
14661
starexec-result
NO
output
/export/starexec/sandbox/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox/benchmark/theBenchmark.smt2 /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- NO Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l4, true> <l1, l2, (1 <= (1 + len_98^0)) /\ (1 <= (0 + len_98^0)) /\ (undef5 = undef5) /\ (undef1 = (0 + l_11^0)) /\ (1 <= (1 + undef5)) /\ (1 <= (0 + undef5)) /\ (undef3 = undef3) /\ (0 <= (0 + (~(1) * undef1))) /\ ((0 + (~(1) * undef1)) <= 0), par{elem_13^0 -> undef1, l_11^0 -> (0 + x_12^0), len_98^0 -> undef3}> <l2, l1, true> <l3, l1, true> <l4, l3, true> Fresh variables: undef1, undef3, undef5, Undef variables: undef1, undef3, undef5, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l1, true> <l1, l1, (1 <= (1 + len_98^0)) /\ (1 <= (0 + len_98^0)) /\ (undef5 = undef5) /\ (undef1 = (0 + l_11^0)) /\ (1 <= (1 + undef5)) /\ (1 <= (0 + undef5)) /\ (undef3 = undef3) /\ (0 <= (0 + (~(1) * undef1))) /\ ((0 + (~(1) * undef1)) <= 0), par{l_11^0 -> (0 + x_12^0), len_98^0 -> undef3}> Fresh variables: undef1, undef3, undef5, Undef variables: undef1, undef3, undef5, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l1, l1, 1 <= len_98^0 /\ 1 <= undef5 /\ l_11^0 = undef1 /\ undef1 = 0, {l_11^0 -> x_12^0, len_98^0 -> undef3, rest remain the same}> Variables: l_11^0, len_98^0, x_12^0 Precedence: Graph 0 Graph 1 <l0, l1, true, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 1 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.002361 Checking conditional termination of SCC {l1}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.000723s LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.002622s [65526 : 65528] [65526 : 65529]
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