Integ Trans Syste 27634 pair #381740141

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details
property value
status complete
benchmark wrong_loop.t2.smt2
ran by Akihisa Yamada
cpu timeout 1200 seconds
wallclock timeout 300 seconds
memory limit 137438953472 bytes
execution host n074.star.cs.uiowa.edu
space From_T2
run statistics
property value
solver VeryMax-termCOMP17
configuration termcomp17
runtime (wallclock) 4.75344896317 seconds
cpu usage 11.109856572
max memory 3.22244608E8
stage attributes
key value
output-size 11924
starexec-result NO
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