Integ Trans Syste 27634 pair #381740162

loading
details
property value
status complete
benchmark insertsort.t2.smt2
ran by Akihisa Yamada
cpu timeout 1200 seconds
wallclock timeout 300 seconds
memory limit 137438953472 bytes
execution host n095.star.cs.uiowa.edu
space From_T2
run statistics
property value
solver VeryMax-termCOMP17
configuration termcomp17
runtime (wallclock) 8.34828805923 seconds
cpu usage 10.447417407
max memory 8.5254144E7
stage attributes
key value
output-size 5678
starexec-result NO
loading output popout

output may be truncated. 'popout' for the full output.

loading job log

	
				popout
			
actions all output return to Integ Trans Syste 27634