details

property	value
status	complete
benchmark	two_arrays1.t2_fixed.smt2
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n096.star.cs.uiowa.edu
space	From_T2

run statistics

property	value
solver	VeryMax-termCOMP17
configuration	termcomp17
runtime (wallclock)	0.0599939823151 seconds
cpu usage	0.05588656
max memory	4489216.0

stage attributes

key	value
output-size	7722
starexec-result	YES

output

/export/starexec/sandbox2/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox2/benchmark/theBenchmark.smt2 /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l19, true> <l1, l2, true> <l3, l4, (50 <= (0 + i^0))> <l3, l5, ((1 + i^0) <= 50), par{i^0 -> (1 + i^0)}> <l6, l7, true> <l8, l5, (50 <= (0 + i17^0)), par{i^0 -> 0}> <l8, l9, ((1 + i17^0) <= 50), par{i17^0 -> (1 + i17^0)}> <l10, l11, true> <l12, l9, (50 <= (0 + i15^0)) /\ (undef73 = 0), par{i17^0 -> 0}> <l12, l13, ((1 + i15^0) <= 50), par{i15^0 -> (1 + i15^0)}> <l14, l15, true> <l16, l13, (50 <= (0 + i13^0)) /\ (undef101 = 0), par{i15^0 -> 0}> <l16, l17, ((1 + i13^0) <= 50), par{i13^0 -> (1 + i13^0)}> <l17, l16, true> <l15, l17, (50 <= (0 + i^0)) /\ (undef129 = 0), par{i13^0 -> 0}> <l15, l14, ((1 + i^0) <= 50), par{i^0 -> (1 + i^0)}> <l13, l12, true> <l11, l14, (50 <= (0 + i11^0)), par{i^0 -> 0}> <l11, l10, ((1 + i11^0) <= 50), par{i11^0 -> (1 + i11^0)}> <l9, l8, true> <l7, l10, (50 <= (0 + i9^0)) /\ (undef184 = 0), par{i11^0 -> 0}> <l7, l6, ((1 + i9^0) <= 50), par{i9^0 -> (1 + i9^0)}> <l5, l3, true> <l2, l6, (50 <= (0 + i7^0)) /\ (undef212 = 0), par{i9^0 -> 0}> <l2, l1, ((1 + i7^0) <= 50), par{i7^0 -> (1 + i7^0)}> <l18, l1, (undef229 = undef229) /\ (undef230 = undef230) /\ (undef231 = 0), par{i7^0 -> 0, i^0 -> 0, tmp^0 -> undef229, tmp___0^0 -> undef230}> <l19, l18, true> Fresh variables: undef73, undef101, undef129, undef184, undef212, undef229, undef230, undef231, Undef variables: undef73, undef101, undef129, undef184, undef212, undef229, undef230, undef231, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l1, (i7^0 = 0) /\ (i^0 = 0) /\ (undef229 = undef229) /\ (undef230 = undef230) /\ (undef231 = 0)> <l1, l6, (50 <= (0 + i7^0)) /\ (undef212 = 0), par{i9^0 -> 0}> <l1, l1, ((1 + i7^0) <= 50), par{i7^0 -> (1 + i7^0)}> <l5, l4, (50 <= (0 + i^0))> <l5, l5, ((1 + i^0) <= 50), par{i^0 -> (1 + i^0)}> <l6, l10, (50 <= (0 + i9^0)) /\ (undef184 = 0), par{i11^0 -> 0}> <l6, l6, ((1 + i9^0) <= 50), par{i9^0 -> (1 + i9^0)}> <l9, l5, (50 <= (0 + i17^0)), par{i^0 -> 0}> <l9, l9, ((1 + i17^0) <= 50), par{i17^0 -> (1 + i17^0)}> <l10, l14, (50 <= (0 + i11^0)), par{i^0 -> 0}> <l10, l10, ((1 + i11^0) <= 50), par{i11^0 -> (1 + i11^0)}> <l13, l9, (50 <= (0 + i15^0)) /\ (undef73 = 0), par{i17^0 -> 0}> <l13, l13, ((1 + i15^0) <= 50), par{i15^0 -> (1 + i15^0)}> <l14, l17, (50 <= (0 + i^0)) /\ (undef129 = 0), par{i13^0 -> 0}> <l14, l14, ((1 + i^0) <= 50), par{i^0 -> (1 + i^0)}> <l17, l13, (50 <= (0 + i13^0)) /\ (undef101 = 0), par{i15^0 -> 0}> <l17, l17, ((1 + i13^0) <= 50), par{i13^0 -> (1 + i13^0)}> Fresh variables: undef73, undef101, undef129, undef184, undef212, undef229, undef230, undef231, Undef variables: undef73, undef101, undef129, undef184, undef212, undef229, undef230, undef231, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: popout

output may be truncated. 'popout' for the full output.

job log

popout

actions

all output return to Integ Trans Syste 27634