details

property	value
status	complete
benchmark	sequential_swap.t2.smt2
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n025.star.cs.uiowa.edu
space	From_T2

run statistics

property	value
solver	VeryMax-termCOMP17
configuration	termcomp17
runtime (wallclock)	0.0221180915833 seconds
cpu usage	0.018217056
max memory	3829760.0

stage attributes

key	value
output-size	2136
starexec-result	YES

output

/export/starexec/sandbox2/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox2/benchmark/theBenchmark.smt2 /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l5, true> <l1, l2, true> <l3, l1, true> <l3, l1, true> <l4, l3, (undef18 = undef18) /\ (undef19 = undef19) /\ (undef20 = undef20), par{i^0 -> 0, j^0 -> 1, tmp1^0 -> undef18, tmp2^0 -> undef19, tmp3^0 -> undef20}> <l5, l4, true> Fresh variables: undef18, undef19, undef20, Undef variables: undef18, undef19, undef20, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l2, (undef18 = undef18) /\ (undef19 = undef19) /\ (undef20 = undef20)> <l0, l2, (undef18 = undef18) /\ (undef19 = undef19) /\ (undef20 = undef20)> Fresh variables: undef18, undef19, undef20, Undef variables: undef18, undef19, undef20, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: Variables: Precedence: Graph 0 Graph 1 <l0, l2, true, {all remain the same}> <l0, l2, true, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Analyzing SCC {l2}... No cycles found. �[32mProgram Terminates�[0m popout

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job log

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actions

all output return to Integ Trans Syste 27634