details

property	value
status	complete
benchmark	consts5nt.t2_fixed.smt2
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n058.star.cs.uiowa.edu
space	From_T2

run statistics

property	value
solver	VeryMax-termCOMP17
configuration	termcomp17
runtime (wallclock)	13.5239400864 seconds
cpu usage	33.829101427
max memory	8.45500416E8

stage attributes

key	value
output-size	3755
starexec-result	NO

output

/export/starexec/sandbox/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox/benchmark/theBenchmark.smt2 /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- NO Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l4, true> <l1, l2, ((1 + y^0) <= 4000) /\ (undef1 = (1000 + x^0)) /\ (111 <= (0 + undef1)), par{x^0 -> undef1}> <l2, l1, true> <l3, l1, true, par{y^0 -> 3000}> <l4, l3, true> Fresh variables: undef1, Undef variables: undef1, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l1, (3000 = 3000)> <l1, l1, ((1 + 3000) <= 4000) /\ (undef1 = (1000 + x^0)) /\ (111 <= (0 + undef1)), par{x^0 -> undef1}> Fresh variables: undef1, Undef variables: undef1, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l1, l1, 111 <= undef1 /\ 1000 + x^0 = undef1, {x^0 -> undef1, rest remain the same}> Variables: x^0 Precedence: Graph 0 Graph 1 <l0, l1, true, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 1 , 1 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility... Time used: 0.001402 Checking conditional termination of SCC {l1}... LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.000528s LOG: CALL solveLinear LOG: RETURN solveLinear - Elapsed time: 0.001850s [27982 : 27990] [27982 : 27991] popout

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job log

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actions

all output return to Integ Trans Syste 27634