details

property	value
status	complete
benchmark	e-acqrel-fail.t2.smt2
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n003.star.cs.uiowa.edu
space	From_T2

run statistics

property	value
solver	VeryMax-termCOMP17
configuration	termcomp17
runtime (wallclock)	4.16186690331 seconds
cpu usage	5.174986857
max memory	1.60137216E8

stage attributes

key	value
output-size	5024
starexec-result	NO

output

/export/starexec/sandbox2/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox2/benchmark/theBenchmark.smt2 /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- NO Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l10, true> <l1, l2, ((0 + dobreak^0) <= 0) /\ (undef5 = 1) /\ (undef4 = undef4) /\ (1 <= (0 + undef4)), par{A^0 -> 0, n^0 -> undef4}> <l1, l3, (1 <= (0 + dobreak^0))> <l4, l1, true> <l2, l5, true> <l6, l7, true> <l3, l8, true> <l8, l3, true> <l5, l2, (1 <= (0 + n^0))> <l5, l4, ((0 + n^0) <= 0) /\ (undef38 = 1) /\ (undef36 = undef36), par{R^0 -> 0, dobreak^0 -> undef36}> <l9, l4, (undef41 = undef41), par{A^0 -> 0, R^0 -> 0, dobreak^0 -> undef41}> <l10, l9, true> Fresh variables: undef4, undef5, undef36, undef38, undef41, Undef variables: undef4, undef5, undef36, undef38, undef41, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l2, (undef41 = undef41) /\ ((0 + undef41) <= 0) /\ (undef5 = 1) /\ (undef4 = undef4) /\ (1 <= (0 + undef4)), par{n^0 -> undef4}> <l0, l3, (undef41 = undef41) /\ (1 <= (0 + undef41))> <l2, l2, (1 <= (0 + n^0))> <l2, l2, ((0 + n^0) <= 0) /\ (undef38 = 1) /\ (undef36 = undef36) /\ ((0 + undef36) <= 0) /\ (undef5 = 1) /\ (undef4 = undef4) /\ (1 <= (0 + undef4)), par{n^0 -> undef4}> <l2, l3, ((0 + n^0) <= 0) /\ (undef38 = 1) /\ (undef36 = undef36) /\ (1 <= (0 + undef36))> <l3, l3, true> Fresh variables: undef4, undef5, undef36, undef38, undef41, Undef variables: undef4, undef5, undef36, undef38, undef41, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l2, l2, 1 <= n^0, {all remain the same}> <l2, l2, n^0 <= 0 /\ undef36 <= 0 /\ 1 <= undef4 /\ undef5 = 1 /\ undef38 = 1, {n^0 -> undef4, rest remain the same}> Variables: n^0 Graph 2: Transitions: <l3, l3, true, {all remain the same}> Variables: Precedence: Graph 0 Graph 1 <l0, l2, undef41 <= 0 /\ 1 <= undef4 /\ undef5 = 1, {n^0 -> undef4, rest remain the same}> Graph 2 <l0, l3, 1 <= undef41, {all remain the same}> <l2, l3, n^0 <= 0 /\ 1 <= undef36 /\ undef38 = 1, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 1 ) popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to Integ Trans Syste 27634