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Integ Trans Syste 27634 pair #381740390
details
property
value
status
complete
benchmark
p-7b.t2.smt2
ran by
Akihisa Yamada
cpu timeout
1200 seconds
wallclock timeout
300 seconds
memory limit
137438953472 bytes
execution host
n072.star.cs.uiowa.edu
space
From_T2
run statistics
property
value
solver
VeryMax-termCOMP17
configuration
termcomp17
runtime (wallclock)
0.0294301509857 seconds
cpu usage
0.026145472
max memory
4227072.0
stage attributes
key
value
output-size
3310
starexec-result
YES
output
/export/starexec/sandbox2/solver/bin/starexec_run_termcomp17 /export/starexec/sandbox2/benchmark/theBenchmark.smt2 /export/starexec/sandbox2/output/output_files -------------------------------------------------------------------------------- YES Solver Timeout: 4 Global Timeout: 300 Maximum number of concurrent processes: 900 No parsing errors! Init Location: 0 Transitions: <l0, l5, true> <l1, l2, (0 <= ((~(1) + (~(1) * x_5^0)) + y_6^0)) /\ ((1 + (~(1) * b_7^0)) <= 0), par{b_7^0 -> 0, y_6^0 -> (~(1) + y_6^0)}> <l1, l3, (((0 + (~(1) * x_5^0)) + y_6^0) <= 0) /\ (undef5 = undef5), par{Result_4^0 -> undef5}> <l4, l2, true, par{b_7^0 -> 0}> <l2, l1, (0 <= ((~(1) + (~(1) * x_5^0)) + y_6^0)) /\ (0 <= (0 + (~(1) * b_7^0))), par{b_7^0 -> 1, x_5^0 -> (1 + x_5^0)}> <l2, l3, (((0 + (~(1) * x_5^0)) + y_6^0) <= 0) /\ (undef17 = undef17), par{Result_4^0 -> undef17}> <l5, l4, true> Fresh variables: undef5, undef17, Undef variables: undef5, undef17, Abstraction variables: Exit nodes: Accepting locations: Asserts: Preprocessed LLVMGraph Init Location: 0 Transitions: <l0, l2, (b_7^0 = 0)> <l2, l2, (0 <= ((~(1) + (~(1) * x_5^0)) + y_6^0)) /\ (0 <= (0 + (~(1) * b_7^0))) /\ (0 <= ((~(1) + (~(1) * (1 + x_5^0))) + y_6^0)) /\ ((1 + (~(1) * 1)) <= 0), par{b_7^0 -> 0, x_5^0 -> (1 + x_5^0), y_6^0 -> (~(1) + y_6^0)}> <l2, l3, (0 <= ((~(1) + (~(1) * x_5^0)) + y_6^0)) /\ (0 <= (0 + (~(1) * b_7^0))) /\ (((0 + (~(1) * (1 + x_5^0))) + y_6^0) <= 0) /\ (undef5 = undef5), par{b_7^0 -> 1, x_5^0 -> (1 + x_5^0)}> <l2, l3, (((0 + (~(1) * x_5^0)) + y_6^0) <= 0) /\ (undef17 = undef17)> Fresh variables: undef5, undef17, Undef variables: undef5, undef17, Abstraction variables: Exit nodes: Accepting locations: Asserts: ************************************************************* ******************************************************************************************* *********************** WORKING TRANSITION SYSTEM (DAG) *********************** ******************************************************************************************* Init Location: 0 Graph 0: Transitions: Variables: Graph 1: Transitions: <l2, l2, b_7^0 <= 0 /\ 2 + x_5^0 <= y_6^0, {b_7^0 -> 0, x_5^0 -> 1 + x_5^0, y_6^0 -> -1 + y_6^0, rest remain the same}> Variables: b_7^0, x_5^0, y_6^0 Graph 2: Transitions: Variables: Precedence: Graph 0 Graph 1 <l0, l2, b_7^0 = 0, {all remain the same}> Graph 2 <l2, l3, b_7^0 <= 0 /\ 1 + x_5^0 = y_6^0, {b_7^0 -> 1, x_5^0 -> 1 + x_5^0, rest remain the same}> <l2, l3, y_6^0 <= x_5^0, {all remain the same}> Map Locations to Subgraph: ( 0 , 0 ) ( 2 , 1 ) ( 3 , 2 ) ******************************************************************************************* ******************************** CHECKING ASSERTIONS ******************************** ******************************************************************************************* Proving termination of subgraph 0 Proving termination of subgraph 1 Checking unfeasibility...
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