details

property	value
status	complete
benchmark	speedNestedMultiple.c.koat
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n046.star.cs.uiowa.edu
space	Flores-Montoya_16

run statistics

property	value
solver	CoFloCo 2018
configuration	its
runtime (wallclock)	1.02505517006 seconds
cpu usage	0.939696566
max memory	1.110016E7

stage attributes

key	value
output-size	14881
starexec-result	WORST_CASE(?,O(n^1))

output

/export/starexec/sandbox/solver/bin/starexec_run_its /export/starexec/sandbox/benchmark/theBenchmark.koat /export/starexec/sandbox/output/output_files -------------------------------------------------------------------------------- WORST_CASE(?,O(n^1)) Preprocessing Cost Relations ===================================== #### Computed strongly connected components 0. recursive : [eval_speedNestedMultiple_6/6,eval_speedNestedMultiple_7/6,eval_speedNestedMultiple_bb2_in/6,eval_speedNestedMultiple_bb3_in/6,eval_speedNestedMultiple_bb4_in/6] 1. recursive : [eval_speedNestedMultiple_11/13,eval_speedNestedMultiple_12/13,eval_speedNestedMultiple__critedge_in/13,eval_speedNestedMultiple_bb1_in/13,eval_speedNestedMultiple_bb2_in_loop_cont/14] 2. non_recursive : [eval_speedNestedMultiple_stop/10] 3. non_recursive : [eval_speedNestedMultiple_bb5_in/10] 4. non_recursive : [exit_location/1] 5. non_recursive : [eval_speedNestedMultiple_bb1_in_loop_cont/11] 6. non_recursive : [eval_speedNestedMultiple_5/10] 7. non_recursive : [eval_speedNestedMultiple_4/10] 8. non_recursive : [eval_speedNestedMultiple_3/10] 9. non_recursive : [eval_speedNestedMultiple_2/10] 10. non_recursive : [eval_speedNestedMultiple_1/10] 11. non_recursive : [eval_speedNestedMultiple_0/10] 12. non_recursive : [eval_speedNestedMultiple_bb0_in/10] 13. non_recursive : [eval_speedNestedMultiple_start/10] #### Obtained direct recursion through partial evaluation 0. SCC is partially evaluated into eval_speedNestedMultiple_bb2_in/6 1. SCC is partially evaluated into eval_speedNestedMultiple_bb1_in/13 2. SCC is completely evaluated into other SCCs 3. SCC is completely evaluated into other SCCs 4. SCC is completely evaluated into other SCCs 5. SCC is partially evaluated into eval_speedNestedMultiple_bb1_in_loop_cont/11 6. SCC is partially evaluated into eval_speedNestedMultiple_5/10 7. SCC is completely evaluated into other SCCs 8. SCC is completely evaluated into other SCCs 9. SCC is completely evaluated into other SCCs 10. SCC is completely evaluated into other SCCs 11. SCC is completely evaluated into other SCCs 12. SCC is completely evaluated into other SCCs 13. SCC is partially evaluated into eval_speedNestedMultiple_start/10 Control-Flow Refinement of Cost Relations ===================================== ### Specialization of cost equations eval_speedNestedMultiple_bb2_in/6 * CE 12 is refined into CE [13] * CE 9 is refined into CE [14] * CE 11 is refined into CE [15] * CE 10 is refined into CE [16] ### Cost equations --> "Loop" of eval_speedNestedMultiple_bb2_in/6 * CEs [16] --> Loop 13 * CEs [13] --> Loop 14 * CEs [14] --> Loop 15 * CEs [15] --> Loop 16 ### Ranking functions of CR eval_speedNestedMultiple_bb2_in(V__1,V_2,V_m,B,C,D) * RF of phase [13]: [-V__1+V_m] #### Partial ranking functions of CR eval_speedNestedMultiple_bb2_in(V__1,V_2,V_m,B,C,D) * Partial RF of phase [13]: - RF of loop [13:1]: -V__1+V_m ### Specialization of cost equations eval_speedNestedMultiple_bb1_in/13 * CE 5 is refined into CE [17] * CE 3 is refined into CE [18,19] * CE 6 is refined into CE [20] * CE 4 is refined into CE [21,22,23,24] ### Cost equations --> "Loop" of eval_speedNestedMultiple_bb1_in/13 * CEs [24] --> Loop 17 * CEs [23] --> Loop 18 * CEs [22] --> Loop 19 * CEs [21] --> Loop 20 * CEs [17] --> Loop 21 * CEs [19] --> Loop 22 * CEs [18] --> Loop 23 * CEs [20] --> Loop 24 ### Ranking functions of CR eval_speedNestedMultiple_bb1_in(V__0,V__01,V__1,V_2,V_5,V_m,V_n,B,C,D,E,F,G) * RF of phase [17,19]: [-V__0+V_n] * RF of phase [20]: [-V__0+V_n] #### Partial ranking functions of CR eval_speedNestedMultiple_bb1_in(V__0,V__01,V__1,V_2,V_5,V_m,V_n,B,C,D,E,F,G) * Partial RF of phase [17,19]: - RF of loop [17:1]: -V__01+V_m-1 - RF of loop [17:1,19:1]: -V__0+V_n * Partial RF of phase [20]: - RF of loop [20:1]: -V__0+V_n popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to Compl Integ Trans Syste 26843