details

property	value
status	complete
benchmark	intersect.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n009.star.cs.uiowa.edu
space	Mixed_AC

run statistics

property	value
solver	AProVE
configuration	standard
runtime (wallclock)	1.68703 seconds
cpu usage	3.21128
user time	3.08143
system time	0.12985
max virtual memory	1.8275288E7
max residence set size	218280.0

stage attributes

key	value
starexec-result	YES

output

3.14/1.64 YES 3.14/1.64 proof of /export/starexec/sandbox2/benchmark/theBenchmark.xml 3.14/1.64 # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty 3.14/1.64 3.14/1.64 3.14/1.64 Termination of the given ETRS could be proven: 3.14/1.64 3.14/1.64 (0) ETRS 3.14/1.64 (1) EDirectTerminationProof [EQUIVALENT, 0 ms] 3.14/1.64 (2) YES 3.14/1.64 3.14/1.64 3.14/1.64 ---------------------------------------- 3.14/1.64 3.14/1.64 (0) 3.14/1.64 Obligation: 3.14/1.64 Equational rewrite system: 3.14/1.64 The TRS R consists of the following rules: 3.14/1.64 3.14/1.64 if(true, x, y) -> x 3.14/1.64 if(false, x, y) -> y 3.14/1.64 eq(0, 0) -> true 3.14/1.64 eq(0, s(x)) -> false 3.14/1.64 eq(s(x), s(y)) -> eq(x, y) 3.14/1.64 union(empty, x) -> x 3.14/1.64 inter(empty, x) -> empty 3.14/1.64 inter(union(y, z), x) -> union(inter(x, y), inter(x, z)) 3.14/1.64 inter(singl(x), singl(y)) -> if(eq(x, y), singl(x), empty) 3.14/1.64 3.14/1.64 The set E consists of the following equations: 3.14/1.64 3.14/1.64 eq(x, y) == eq(y, x) 3.14/1.64 inter(x, y) == inter(y, x) 3.14/1.64 union(x, y) == union(y, x) 3.14/1.64 inter(inter(x, y), z) == inter(x, inter(y, z)) 3.14/1.64 union(union(x, y), z) == union(x, union(y, z)) 3.14/1.64 3.14/1.64 3.14/1.64 ---------------------------------------- 3.14/1.64 3.14/1.64 (1) EDirectTerminationProof (EQUIVALENT) 3.14/1.64 We use [DA_FALKE] with the following order to prove termination. 3.14/1.64 3.14/1.64 Precedence: 3.14/1.64 s_1 > false 3.14/1.64 inter_2 > if_3 3.14/1.64 inter_2 > eq_2 > true 3.14/1.64 inter_2 > union_2 3.14/1.64 singl_1 > empty 3.14/1.64 3.14/1.64 3.14/1.64 Status: 3.14/1.64 inter_2: flat status 3.14/1.64 union_2: flat status 3.14/1.64 eq_2: flat status 3.14/1.64 3.14/1.64 3.14/1.64 3.14/1.64 ---------------------------------------- 3.14/1.64 3.14/1.64 (2) 3.14/1.64 YES 3.14/1.68 EOF popout

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all output return to TRS_Equational 2019-03-21 05.09