details

property	value
status	complete
benchmark	PEANO_complete_noand_C.xml
ran by	Akihisa Yamada
cpu timeout	1200 seconds
wallclock timeout	300 seconds
memory limit	137438953472 bytes
execution host	n148.star.cs.uiowa.edu
space	Transformed_CSR_innermost_04

run statistics

property	value
solver	AProVE
configuration	standard
runtime (wallclock)	2.89475 seconds
cpu usage	7.62904
user time	7.26901
system time	0.36003
max virtual memory	1.8409116E7
max residence set size	461252.0

stage attributes

key	value
starexec-result	YES

output

7.19/2.75 YES 7.43/2.77 proof of /export/starexec/sandbox2/benchmark/theBenchmark.xml 7.43/2.77 # AProVE Commit ID: 48fb2092695e11cc9f56e44b17a92a5f88ffb256 marcel 20180622 unpublished dirty 7.43/2.77 7.43/2.77 7.43/2.77 Termination w.r.t. Q of the given QTRS could be proven: 7.43/2.77 7.43/2.77 (0) QTRS 7.43/2.77 (1) QTRSToCSRProof [SOUND, 0 ms] 7.43/2.77 (2) CSR 7.43/2.77 (3) CSRRRRProof [EQUIVALENT, 87 ms] 7.43/2.77 (4) CSR 7.43/2.77 (5) CSRRRRProof [EQUIVALENT, 20 ms] 7.43/2.77 (6) CSR 7.43/2.77 (7) CSRRRRProof [EQUIVALENT, 15 ms] 7.43/2.77 (8) CSR 7.43/2.77 (9) CSRRRRProof [EQUIVALENT, 23 ms] 7.43/2.77 (10) CSR 7.43/2.77 (11) CSRRRRProof [EQUIVALENT, 13 ms] 7.43/2.77 (12) CSR 7.43/2.77 (13) CSRRRRProof [EQUIVALENT, 0 ms] 7.43/2.77 (14) CSR 7.43/2.77 (15) CSRRRRProof [EQUIVALENT, 10 ms] 7.43/2.77 (16) CSR 7.43/2.77 (17) CSRRRRProof [EQUIVALENT, 0 ms] 7.43/2.77 (18) CSR 7.43/2.77 (19) CSRRRRProof [EQUIVALENT, 0 ms] 7.43/2.77 (20) CSR 7.43/2.77 (21) CSRRRRProof [EQUIVALENT, 7 ms] 7.43/2.77 (22) CSR 7.43/2.77 (23) CSRRRRProof [EQUIVALENT, 0 ms] 7.43/2.77 (24) CSR 7.43/2.77 (25) CSRRRRProof [EQUIVALENT, 6 ms] 7.43/2.77 (26) CSR 7.43/2.77 (27) CSRRRRProof [EQUIVALENT, 0 ms] 7.43/2.77 (28) CSR 7.43/2.77 (29) CSRRRRProof [EQUIVALENT, 0 ms] 7.43/2.77 (30) CSR 7.43/2.77 (31) CSRRRRProof [EQUIVALENT, 0 ms] 7.43/2.77 (32) CSR 7.43/2.77 (33) CSRRRRProof [EQUIVALENT, 0 ms] 7.43/2.77 (34) CSR 7.43/2.77 (35) CSRRRRProof [EQUIVALENT, 2 ms] 7.43/2.77 (36) CSR 7.43/2.77 (37) RisEmptyProof [EQUIVALENT, 0 ms] 7.43/2.77 (38) YES 7.43/2.77 7.43/2.77 7.43/2.77 ---------------------------------------- 7.43/2.77 7.43/2.77 (0) 7.43/2.77 Obligation: 7.43/2.77 Q restricted rewrite system: 7.43/2.77 The TRS R consists of the following rules: 7.43/2.77 7.43/2.77 active(U11(tt, V1, V2)) -> mark(U12(isNatKind(V1), V1, V2)) 7.43/2.77 active(U12(tt, V1, V2)) -> mark(U13(isNatKind(V2), V1, V2)) 7.43/2.77 active(U13(tt, V1, V2)) -> mark(U14(isNatKind(V2), V1, V2)) 7.43/2.77 active(U14(tt, V1, V2)) -> mark(U15(isNat(V1), V2)) 7.43/2.77 active(U15(tt, V2)) -> mark(U16(isNat(V2))) 7.43/2.77 active(U16(tt)) -> mark(tt) 7.43/2.77 active(U21(tt, V1)) -> mark(U22(isNatKind(V1), V1)) 7.43/2.77 active(U22(tt, V1)) -> mark(U23(isNat(V1))) 7.43/2.77 active(U23(tt)) -> mark(tt) 7.43/2.77 active(U31(tt, V2)) -> mark(U32(isNatKind(V2))) 7.43/2.77 active(U32(tt)) -> mark(tt) 7.43/2.77 active(U41(tt)) -> mark(tt) 7.43/2.77 active(U51(tt, N)) -> mark(U52(isNatKind(N), N)) 7.43/2.77 active(U52(tt, N)) -> mark(N) 7.43/2.77 active(U61(tt, M, N)) -> mark(U62(isNatKind(M), M, N)) 7.43/2.77 active(U62(tt, M, N)) -> mark(U63(isNat(N), M, N)) 7.43/2.77 active(U63(tt, M, N)) -> mark(U64(isNatKind(N), M, N)) 7.43/2.77 active(U64(tt, M, N)) -> mark(s(plus(N, M))) 7.43/2.77 active(isNat(0)) -> mark(tt) 7.43/2.77 active(isNat(plus(V1, V2))) -> mark(U11(isNatKind(V1), V1, V2)) 7.43/2.77 active(isNat(s(V1))) -> mark(U21(isNatKind(V1), V1)) 7.43/2.77 active(isNatKind(0)) -> mark(tt) 7.43/2.77 active(isNatKind(plus(V1, V2))) -> mark(U31(isNatKind(V1), V2)) 7.43/2.77 active(isNatKind(s(V1))) -> mark(U41(isNatKind(V1))) 7.43/2.77 active(plus(N, 0)) -> mark(U51(isNat(N), N)) 7.43/2.77 active(plus(N, s(M))) -> mark(U61(isNat(M), M, N)) 7.43/2.77 active(U11(X1, X2, X3)) -> U11(active(X1), X2, X3) 7.43/2.77 active(U12(X1, X2, X3)) -> U12(active(X1), X2, X3) 7.43/2.77 active(U13(X1, X2, X3)) -> U13(active(X1), X2, X3) 7.43/2.77 active(U14(X1, X2, X3)) -> U14(active(X1), X2, X3) 7.43/2.77 active(U15(X1, X2)) -> U15(active(X1), X2) 7.43/2.77 active(U16(X)) -> U16(active(X)) 7.43/2.77 active(U21(X1, X2)) -> U21(active(X1), X2) 7.43/2.77 active(U22(X1, X2)) -> U22(active(X1), X2) 7.43/2.77 active(U23(X)) -> U23(active(X)) 7.43/2.77 active(U31(X1, X2)) -> U31(active(X1), X2) 7.43/2.77 active(U32(X)) -> U32(active(X)) 7.43/2.77 active(U41(X)) -> U41(active(X)) 7.43/2.77 active(U51(X1, X2)) -> U51(active(X1), X2) 7.43/2.77 active(U52(X1, X2)) -> U52(active(X1), X2) 7.43/2.77 active(U61(X1, X2, X3)) -> U61(active(X1), X2, X3) 7.43/2.77 active(U62(X1, X2, X3)) -> U62(active(X1), X2, X3) 7.43/2.77 active(U63(X1, X2, X3)) -> U63(active(X1), X2, X3) 7.43/2.77 active(U64(X1, X2, X3)) -> U64(active(X1), X2, X3) 7.43/2.77 active(s(X)) -> s(active(X)) popout

output may be truncated. 'popout' for the full output.

job log

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actions

all output return to TRS_Innermost 2019-03-28 22.12